The use of a 4F2 cell configuration is very typical in emerging memory devices to enable higher densification and implementation of cross-point memory architecture. The pitch scaling as well as the device performance of these memories mainly rely on the patterning process of the orthogonal array vertical pillars. In this paper, we screen several lithography approaches to optimize the 36nm and 34nm pitch pillar patterning using single exposure EUV (extreme ultraviolet) lithography. The main process knobs used for this screening work are the UL (underlayer) material selection and different flavors of the ESPERTTM photoresist development process from TELTM. The results for 34nm pitch with 17nm target CD show that LCDU can be improved from 1.77nm to 1.53nm with a similar dose-to-size requirement and slightly better WCDU for ESPERTTM 3 process in SiC compared to imec POR process. For 36nm pitch, on the other hand, with 18nm ADI CD target, LCDU has been improved from 1.68nm to 1.47nm with a similar WCDU and slightly lower dose-to-size. Moreover, the failure rate for missing and bridging pillars is much lower for ESPERTTM 3 compared to our reference process for both 34nm and 36nm pitch process.
The use of a 4F2 cell configuration which enables higher densification is common in emerging memory devices. The pitch scaling and the robustness of these devices mainly rely on the patterning of the orthogonal array vertical pillar process. In this paper, we screen several lithography process approaches to optimize the 40nm pitch pillar patterning using single exposure EUV (extreme ultraviolet) lithography. The results show that with the optimized 40nm pitch process roughly 0.6nm 3-Sigma WCDU (wafer critical dimension uniformity) and 1.4nm 3-Sigma LCDU (local critical dimension uniformity) can be obtained post-litho for 21.1nm mean CD (critical dimension). Post-etch patterning with the best process shows 1.8nm 3-Sigma WCDU and 1.3nm 3-Sigma LCDU at 17.2nm mean CD. Smaller pitches have also been explored to identify the limits of the single EUV lithography process. Structures at 34nm pitch have shown high amount of pillar collapse. For 36nm pitch, on the other hand, a reasonable litho performance could be obtained with slightly boosted CD. The post-litho results show that with the optimized 36nm pitch process 0.4nm 3-Sigma WCDU and 1.4nm 3-Sigma LCDU can be obtained for 19.1nm mean CD.
The read performance of a spin-transfer torque magnetic random-access memory device is based on the tunnel magnetoresistance of the magnetic tunnel junction cell, which is a function of the resistance values at low and high resistance states of the magnetic layers. To ensure a robust tunnel magnetoresistance value and high yield, magnetic tunnel junction pillar patterning process should have a good local critical dimension uniformity. In this paper, we screen several patterning techniques, such as dry development rinse material-based tone reversal besides the standard patterning, as well as different resists and underlayer materials to improve the local critical dimension uniformity at 50nm pitch extreme ultraviolet pillar printing. The results of the best litho process obtained show an improvement above 20% for the local critical dimension uniformity performance. The performance metrics such as the process windows analysis, pillar circularity and the critical dimension uniformity have also been checked for the promising litho process options. Moreover, the transfer of the post-litho improvements to the etch process have been checked and qualified after several layers of hardmask etch.
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