Lithographic process steps used in today's integrated circuit production require tight control of critical
dimensions (CD). With new design rules dropping to 32 nm and emerging double patterning processes,
parameters that were of secondary importance in previous technology generations have now become
determining for the overall CD budget in the wafer fab. One of these key parameters is the intra-field mask
CD uniformity (CDU) error, which is considered to consume an increasing portion of the overall CD
budget for IC fabrication process. Consequently, it has become necessary to monitor and characterize CDU
in both the maskshop and the wafer fab.
Here, we describe the introduction of a new application for CDU monitoring into the mask making process
at Samsung. The IntenCD<sup>TM</sup> application, developed by Applied Materials, is implemented on an aerial
mask inspection tool. It uses transmission inspection data, which contains information about CD variation
over the mask, to create a dense yet accurate CDU map of the whole mask. This CDU map is generated in
parallel to the normal defect inspection run, thus adding minimal overhead to the regular inspection time.
We present experimental data showing examples of mask induced CD variations from various sources such
as geometry, transmission and phase variations. We show how these small variations were captured by
IntenCD<sup>TM</sup> and demonstrate a high level of correlation between CD SEM analysis and IntenCD<sup>TM</sup> mapping
of mask CDU. Finally, we suggest a scheme for integrating the IntenCD<sup>TM</sup> application as part of mask
qualification procedure at maskshops.
As feature size continuously decreasing new techniques to improve quality of wafer are developed. Hence a lot of new
problems in semiconductor industry arise. Strict control of quality of wafer during production process is very important
as many factors can influence on it, but the main contribution gives scanner error and mask. Thus at least impact of mask
should be reduced.
In this work we apply rigorous model to predict impact of microstructures to pattern fidelity on wafer. Such
microstructures are commonly generated in quartz layer to control transmittance distribution on photomask. It is shown
that effect from microstructures is not only changing of mask transmittance but also distortion of the pattern fidelity on
wafer. Rigorous modeling gives us possibility to calculate aerial image and CD on wafer in case of presence of microstructures
in the quartz. We vary optical parameters, such as refractive indexes, number, size and location of these
elements in order to reduce the distortion of pattern fidelity on wafer.
Our result allows prediction of the impact of microstructures in photomask on wafer pattern fidelity instead of doing set
of experiments. Moreover, the best conditions for experiment are found and discussed.
In the ArF lithography for sub-100nm, PSM (Phase Shift Mask) has been considered as one of the basic RETs (Resolution Enhancement Techniques). Nowadays, besides attenuated PSM, alternating PSM and CPL (Chromeless Phase Lithography) containing Cr patch is widely studied for targeting sub-100nm. Since 2nd process using 365nm laser tools for Cr patch has been a wide gap between the reality and the demands, various candidates using 254nm laser or e-beam exposure tool have been presented to overcome the current 2nd process limitation. And, the Cr patch operate as an assist pattern to control the transmittance of mask, therefore, the CPL mask with Cr patch have advantages of improving process margin such as dose margin and its applicable flexibility for various layers, dense or isolated pattern in the memory and logic device. In this paper, we scrutinize the feasibility of 2nd alignment using 10keV e-beam. Process issues such as the charging effects caused by 2nd e-beam exposure on the 1st Cr etched substrate were evaluated as well.