Extreme ultraviolet (EUV) lithography is the technology for high volume manufacturing (HVM) of semiconductor ICs for photoresist patterns smaller than 75nm pitch¹. A persistent challenge of the EUV scanner is to supply a high contrast image with enough photons to the photoresist (PR) to meet HVM productivity targets with acceptable dimensional and defectivity control. Local stochastic variability in dimension and placement dominates the total dimension control budget and reducing that variability by increasing the exposure dose comes at the cost of scanner throughput. Our objective is to deliver holistic patterning solutions by co-optimization of patterning film stack, lithography, and subsequent etch processes to transfer the patterns to the target layer with CD and placement control of order 1nm or less! This synergistic approach enables circuit fabrication customers to manage the tradeoff between stochastic defects and productivity in EUV patterning.
Extending extreme ultraviolet (EUV) single exposure patterning to its limits is dependent on eliminating its stochastic defectivity. Along with developments in photoresist platforms, the patterning film stack also needs to be considered. The material immediately underneath the photoresist is expected to have significant impact on both lithographic and pattern transfer performance. By designing the resist substrate interface with high EUV absorbance, there is potential to increase the EUV quantum yield of the exposure process. This paper will demonstrate the patterning of a chemically amplified resist on a high-Z metal-based hardmask. The potential for dose reduction, higher etch selectivity, and defectivity improvement from a high-Z hardmask will be discussed. Deposition-trim etch techniques will be used for decreasing the transfer of stochastic defects to the underlying substrate. Sub-32nm pitch trench patterning, defectivity, and electrical yield for this patterning stack will be highlighted.
Despite the innumerable advances in EUV lithography for materials, optics, and process in recent years, the N7 and N5 targets for resolution, line roughness, and sensitivity (RLS, collectively) have not simultaneously been achieved from both a yield and cost perspective due to their interdependent nature. For example, reducing dose to an economically practical level results in resolution and roughness levels that generate unacceptable yield and performance. These limitations have traditionally been viewed in a light where only conventional post-lithographic processing by etch is used for the subsequent pattern transfer. Recent post-lithography defect mitigation techniques, however, combine the use of high etch selectivity underlayers, atomic layer etch (ALE) descum, and fast-switching deposition and etch resist linespace pattern repair have overcome the limitations of the RLS interdependency by correcting for resolution and stochastics related defects and improving LER associated with lower exposure dose . Here, an aspect ratio dependent deposition can be used to protect the resist lines from further notching and damage while allowing for residual scum between the lines to be etched . A lithography, etch, and metrology feedback loop can be envisioned in which a minimum dose requirement is found where both the LER and lithography related defects are still correctable using post-exposure processing; however, due to the extremely long metrology times for e-beam inspection combined with the large quantity of adjustable parameters, traditional experimental DOEs quickly become unmanageable. The intractability of this situation necessitates a simulation-based parameter space optimization to reduce the required number of feedback cycles. In this study, Coventor SEMulator3D® is used to find optimized solutions for minimizing resist line bridges and breaks as well as line smoothing. Here, distributions of line roughness and resist divot and scum dimensions can be subjected to simulated process recipes with tunable parameters like etch selectivities, aspect ratio dependence of deposition and etch, deposition and etch rates, number of ALE cycles, etc. that one would typically explore in this defect mitigation strategy. The resulting defects can then be analyzed to determine how each defect in the distribution reacts to a given treatment. Additionally, further insight can be gleaned regarding the types and dimensions of defects that can be corrected and that would otherwise not be measurable using any physical metrology. For example, at low dose, a portion of the defect size distribution is comparable to the drawn features and can no longer be corrected by the post-exposure treatment. Due to the randomness of the defects and small size, three-dimensional characterization is difficult, but using simulation, it is possible to show at what dimension the defect mitigation strategy begins to fail.
Continued improvement in pattern fidelity and reduction in total edge placement errors are critical to enable yield and scaling in advanced devices. In this work, we discuss patterning optimization in a combined two-layer process, using ArFi self-aligned double patterned line and EUV via process in a 10nm test vehicle. In prior work (1), we showed the composite correction ability for lithography and etch systems in single layer processes. Here, we expand on the optimization and setup to improve the single layer process, improve the line edge roughness, and look at a second layer via process. The sum of all those optimizations is the edge placement. Here, we describe the fidelity of the final multilayer pattern and the process budget for a two-layer line and via process in terms of total edge placement error (EPE) (2). In the line process, control of mechanical interactions in the resist and etch process significantly improve line width and line edge roughness (LWR/LER), with a net improvement in LWR of 30% measured after develop, and 18% measured after etch. Pitchwalk is improved using cross wafer etch and litho cooptimization to less than 1.0nm 3σ. For the via process, we determine the root distribution of EPE resulting from the core placement errors at lithography and etch. Results on final multilayer pattern uniformity, overlay, and edge placement are shown.
Edge placement error (EPE) has become an increasingly critical metric to enable Moore’s Law scaling. Stochastic variations, as characterized for lines by line width roughness (LWR) and line edge roughness (LER), are dominant factors in EPE and known to increase with the introduction of EUV lithography. However, despite recommendations from ITRS, NIST, and SEMI standards, the industry has not agreed upon a methodology to quantify these properties. Thus, differing methodologies applied to the same image often result in different roughness measurements and conclusions. To standardize LWR and LER measurements, Fractilia has developed an unbiased measurement that uses a raw unfiltered line scan to subtract out image noise and distortions. By using Fractilia’s inverse linescan model (FILM) to guide development, we will highlight the key influences of roughness metrology on plasma-based resist smoothing processes. Test wafers were deposited to represent a 5 nm node EUV logic stack. The patterning stack consists of a core Si target layer with spin-on carbon (SOC) as the hardmask and spin-on glass (SOG) as the cap. Next, these wafers were exposed through an ASML NXE 3350B EUV scanner with an advanced chemically amplified resist (CAR). Afterwards, these wafers were etched through a variety of plasma-based resist smoothing techniques using a Lam Kiyo conductor etch system. Dense line and space patterns on the etched samples were imaged through advanced Hitachi CDSEMs and the LER and LWR were measured through both Fractilia and an industry standard roughness measurement software. By employing Fractilia to guide plasma-based etch development, we demonstrate that Fractilia produces accurate roughness measurements on resist in contrast to an industry standard measurement software. These results highlight the importance of subtracting out SEM image noise to obtain quicker developmental cycle times and lower target layer roughness.
Extreme ultraviolet (EUV) lithography is crucial to enabling technology scaling in pitch and critical dimension (CD). Currently, one of the key challenges of introducing EUV lithography to high volume manufacturing (HVM) is throughput, which requires high source power and high sensitivity chemically amplified photoresists. Important limiters of high sensitivity chemically amplified resists (CAR) are the effects of photon shot noise and resist blur on the number of photons received and of photoacids generated per feature, especially at the pitches required for 7 nm and 5 nm advanced technology nodes. These stochastic effects are reflected in via structures as hole-to-hole CD variation or local CD uniformity (LCDU). Here, we demonstrate a synergy of film stack deposition, EUV lithography, and plasma etch techniques to improve LCDU, which allows the use of high sensitivity resists required for the introduction of EUV HVM. Thus, to improve LCDU to a level required by 5 nm node and beyond, film stack deposition, EUV lithography, and plasma etch processes were combined and co-optimized to enhance LCDU reduction from synergies. <p> </p>Test wafers were created by depositing a pattern transfer stack on a substrate representative of a 5 nm node target layer. The pattern transfer stack consisted of an atomically smooth adhesion layer and two hardmasks and was deposited using the Lam VECTOR PECVD product family. These layers were designed to mitigate hole roughness, absorb out-of-band radiation, and provide additional outlets for etch to improve LCDU and control hole CD. These wafers were then exposed through an ASML NXE3350B EUV scanner using a variety of advanced positive tone EUV CAR. They were finally etched to the target substrate using Lam Flex dielectric etch and Kiyo conductor etch systems. Metrology methodologies to assess dimensional metrics as well as chip performance and defectivity were investigated to enable repeatable patterning process development. <p> </p>Illumination conditions in EUV lithography were optimized to improve normalized image log slope (NILS), which is expected to reduce shot noise related effects. It can be seen that the EUV imaging contrast improvement can further reduce post-develop LCDU from 4.1 nm to 3.9 nm and from 2.8 nm to 2.6 nm. In parallel, etch processes were developed to further reduce LCDU, to control CD, and to transfer these improvements into the final target substrate. We also demonstrate that increasing post-develop CD through dose adjustment can enhance the LCDU reduction from etch. Similar trends were also observed in different pitches down to 40 nm. The solutions demonstrated here are critical to the introduction of EUV lithography in high volume manufacturing. It can be seen that through a synergistic deposition, lithography, and etch optimization, LCDU at a 40 nm pitch can be improved to 1.6 nm (3-sigma) in a target oxide layer and to 1.4 nm (3-sigma) at the photoresist layer.
With shrinking design rules, the overall patterning requirements are getting aggressively tighter. For the 7-nm node and below, allowable CD uniformity variations are entering the Angstrom region (ref ). Optimizing inter- and intra-field CD uniformity of the final pattern requires a holistic tuning of all process steps. In previous work, CD control with either litho cluster or etch tool corrections has been discussed. Today, we present a holistic CD control approach, combining the correction capability of the etch tool with the correction capability of the exposure tool. The study is done on 10-nm logic node wafers, processed with a test vehicle stack patterning sequence. We include wafer-to-wafer and lot-to-lot variation and apply optical scatterometry to characterize the fingerprints. Making use of all available correction capabilities (lithography and etch), we investigated single application of exposure tool corrections and of etch tool corrections as well as combinations of both to reach the lowest CD uniformity. Results of the final pattern uniformity based on single and combined corrections are shown. We conclude on the application of this holistic lithography and etch optimization to 7nm High-Volume manufacturing, paving the way to ultimate within-wafer CD uniformity control.
A double patterning (DP) process is introduced with application for advanced technology nodes. This DP technique is enabled by a novel low-temperature pulsed deposition layer (PDL<sup>TM</sup>) oxide film which is deposited directly on patterned photoresist. In this article, we will report the results of fabrication of sub-50nm features on a 100nm pitch by the PDL-spacer DP process using 0.85 NA dry ArF lithography. This result represents the potential of the PDL-based DP to significantly enhance the resolution of the patterning process beyond the limits of optical lithography. Components of CD variance for this spacer DP scheme will be discussed.
Aggressive line width control requirements for leading edge IC fabrication necessitate integration of novel techniques such as DoseMapper into the lithography process flow. DoseMapper is based on the simple concept that CD uniformity (CDU) can be improved through compensation of CD errors by using the scanner actuators. Specifically, the DoseMapper system allows for compensation of interfield and intrafield CD non-uniformity, based on the spatial distribution of in-line CD measurements or end-of-line electrical parameters for a stable process. This approach is supported by the fact that small variations of linewidth are correlated to exposure dose in a linear fashion. In this work we describe strategies for and results of the application of DoseMapper in a lithographic process for gate layer in a 65nm technology. We will highlight the potential strengths and weaknesses of various DoseMapper strategies to. For instance, we have learned that dose adjustments which are based on post-etch CD signature can lead to degradation of the lithography-based process window especially for 2 -dimensional features due to high MEEF. Therefore, it is asserted that application of DoseMapper in a high-volume manufacturing process requires consideration of such rational tradeoffs as mentioned above. Impact of Mask CD variation on DoseMapper effectiveness will also be discussed. This has the potential to have a significant impact on manufacturability of photo masks for the 65nm node and beyond
Inverse Lithography Technology (ILT), a mask creation technique with a decades-long history, has the potential for improving pattern fidelity and lithographic process window for features in dense memory ce lls (such as SRAM) for 100nm and 65nm nodes and beyond. Currently, the quality of OPC/RET/DfM/DfY methodology is verified based on CD
measurements. However, these measurements are not comprehensive enough, limited to a very few layout features. It is desirable to confirm lithographic process window robustly, for all the cell design features of interest, to ensure full functionality of the cell. In this work, we propose for the first time to focus on the electrical deliverables after ILT pattern quality has been initially verified by SEM visual inspection. We designed an electrically measurable SRAM
structure for a 65 nm process, to extract device and interconnect parameters depending on the lithographic process conditions, as a means to compare pattern quality of the conventional mask creation technique, Optical Proximity Correction (OPC) with ILT. We present the drawn layout, the masks created by the two technologies, and the
corresponding image simulation and silicon pattern.
This paper presents ILT masks written by a DUV laser writer and a VSB e-beam writer, and their corresponding wafer print results. ILT mathematically determine the mask features that produce the desired on-wafer results. ILT-generated masks sometimes are non-intuitive, and different than those produced by past approaches; therefore, their manufacturability must be understood. In this study ILT was applied to create binary chrome-on-glass (CoG) masks with feature sizes ranging from 130 nm to 45 nm (at the wafer scale). The masks were written with both DUV laser (AMAT Alta 4300) and electron beam (JEOL JBX-9000) pattern generators. Wafers were then printed on a 193 nm scanner (ASML 1400, NA = 0.75). Mask image quality and wafer image quality (SEM micrographs and focus-exposure CD performance) were collected. In addition, it was also demonstrated that ILT has the capability to tune the mask complexity by constraining fracture figure size and the minimum mask feature/space.
This paper presents SMIC's first 65nm tape out results, in particularly, using ILT. ILT mathematically determines the mask features that produce the desired on-wafer results with best wafer pattern fidelity, largest process window or both. SMIC applied it to its first 65nm tape-out to study ILT performance and benefits for deep sub-wavelength lithography. SMIC selected 3 SRAM designs as the first test case, because SRAM bit-cells contain features which are challenging lithographically. Mask patterns generated from both conventional OPC and ILT were placed on the mask side-by-side. Mask manufacturability (including fracturing, writing time, inspection, and metrology) and wafer print performance of ILT were studied. The results demonstrated that ILT achieved better CD accuracy, produced substantially larger process window than conventional OPC, and met SMIC's 65nm process window requirements.
In the development and manufacture of integrated circuits, as requirements push closer to the theoretical (Rayleigh) limit of performance, depth of focus decreases as resolution is increased. The advent of easily accessible tools for image processing suggest that a quantitative determination of best focus is possible. Workers in this laboratory have developed a technique for determining `best focus' using 2-D Fourier power spectra of SEM images of exposed patterns. From this a `figure of merit' is extracted by assuming that what is desired is to maximize orthogonal edges (from `as-drawn' features) and minimize intermediate features (edge rounding). This has been shown to provide a quantitative value that is consistent with an `expert' assessment of the same images. The system is consistent with automation of the process, eliminating the need to record hard-copy images for `expert' evaluation.