The statistical characterization and reliability results for a One Time Programmable (OTP) non-volatile memory that uses a p-type cobalt salicide polysilicon (CoSi<sub>2</sub>) fuse for a 0.25μm technology are presented. The fuse element consists of a minimum width 80 Ohm poly resistor with rectangular head connections surrounded by oxynitride and passivating oxide layers. A low resistance transistor is used to control the programming voltage rise and fall time of the fuse. The chosen programming voltage and time at 27°C causes local Joule heating and electromigration of the Cobalt with dissolution of the polysilicon and diffusion of the p-type dopant to the anode. A characterization methodology was developed for determining the optimum programming conditions to form an amorphous, void free fuse with a final resistance of greater than 1MOhm without disturbing the passivating films. The process window characterization showed that thinner CoSi<sub>2</sub> films resulted in significant reduction of partially blown fuses in the tail of the resistance distributions. The JEDEC HTOL/HTSL specified methods were used to stress 3.9 million programmed fuses at 125°C/150°C for up to 2000 hours which resulted in no bit failures for three lots tested. The resistance drift for programmed fuses after thermal and electrical stress showed no significant change in the distributions.
A methodology and a Monte Carlo simulation flow with integrated LSI Logic's OPC package, Molotof, was applied to the 65nm poly line sensitivity analysis. Strong phase shift mask (sPSM) manufacturing specifications were optimized to obtain image critical dimensions (CD) and image placement errors (IPE) complying with technology design rules. Reticle manufacturing statistical errors of phase depth, phase width, and phase intensity imbalance were used to generate a virtual sPSM for imaging poly lines. A criterion for qualifying reticle specification is to obtain all latent image CDs and IPEs within a design rule allowed range for a given mask specification. The approach allows for computing reticle and litho budgets into CD imaging performance. We present simulation and empirical results of statistical analysis of the 65nm poly line (clear field) printability, and a method for optimizing a strong phase shift reticle specification. Sensitivity to a single parameter variation and full statistical analysis of the 65nm poly line imaging performance affected by manufacturing errors is presented. The optimum reticle specification, yielded 100% of critical dimensions and image placement errors, was found in simulation and confirmed by empirical data.
Optical proximity correction (OPC) procedure for modifying designs requires an OPC setting effectively accounting for manufacturing and imaging constraints. Reticle-writing and imaging tool capabilities drive the choice for the minimum feature of an OPC model.
Aggressiveness of an optical proximity correction is determined by a discretization setting for an OPC algorithm. Some OPC scheme parameters are there to restrict the minimum spacing and width to avoid circuit failures. The OPC minimum spacing parameter controls bridging lines. The OPC minimum width parameter limits the correction of trenches responsible for circuit breakdown. An aggressive choice of minimum spacing and width for an OPC setting can results in circuit failure: shortage or breakdown. The conservative approach results in poor circuit performance.
The methodology was deployed at LSI Logic Corporation for empirical optimization of the OPC minimum spacing/width settings for a no failure imaging solution of OPCed masks. The proposed procedure is particularly beneficial for dark field metal interconnect masks. The approach was successfully validated for 130nm and 90nm backend technology metal layers.
A methodology has been developed to measure OPC model robustness as a function of systematic and statistical process variations. The analysis includes comparison of imaging solutions with several different OPC models generated for different writing tools and lithography process conditions. This approach allows for definition of OPC model tolerance in the continually changing R&D and production environment. The question of when it is absolutely necessary to regenerate OPC models and when application of "the old" OPC model is acceptable is answered
This method has been applied at LSI Logic for qualifying a single OPC model for e-beam and laser reticle writing tools in back-end processes for the 0.13um technology node. The OPC model tolerance qualification takes additional time and engineering effort, but it provides pay back through comparable or better product performance and lower costs.
LSI Logic's OPC package, Molotof, integrated into several RET flows has been successfully applied for strong phase shift mask simulation and optimization. Molotof simulator was used to predict sPSM imaging performance in response to statistical errors of alternating phase shift reticle manufacturing. Mask manufacturing errors were reproduced by generating a virtual gds mask with random values of sPSM control parameters such as phase depth, phase width and phase intensity. By measuring critical dimensions and image placement errors of a simulated aerial image for each random event, the image printability performance was calculated. The approach allows for quantitative evaluation and optimization of a strong PSM manufacturing specification by analyzing the distributions of critical dimensions and image placement errors. 2D-model, metrology and simulation flow for performing statistical analysis are discussed. Sensitivity to a single parameter variation and full statistical analysis of the 90nm poly line imaging performance affected by manufacturing errors is presented. The optimum range of phase depth, phase width and phase intensity, yielded 100% of critical dimensions and image placement errors, complying with 90nm technology design rules was found in simulation. Simulation results are confirmed by empirical data.
The complexity of current semiconductor technology due to shrinking feature sizes causes more and more engineering efforts and expenses to deliver the final product to customers. One of the largest expense in the entire budget is the reticle manufacturing. With the need to perform mask correction in order to account for optical proximity effects on the wafer level, the reticle expenses have become even more critical. For 0.13um technology one can not avoid optical proximity correction (OPC) procedure for modifying original designs to comply with design rules as required by Front End (FE) and Back End (BE) processes. Once an OPC model is generated one needs to confirm and verify the said model with additional test reticles for every critical layer of the technology. Such a verification procedure would include the most critical layers (two FE layers and four BE layers for the 0.13 technology node). This allows us to evaluate model performance under real production conditions encountered on customer designs. At LSI we have developed and verified the low volume reticle (LVR) approach for verification of different OPC models. The proposed approach allows performing die-to-die reticle defect inspection in addition to checking the printed image on the wafer. It helps finalizing litho and etch process parameters. Processing wafers with overlaying masks for two consecutive BE layer (via and metal2 masks) allowed us to evaluate robustness of OPC models for a wafer stack against both reticle and wafer induced misalignments.
The challenge of delivering acceptable semiconductor products to customers in timely fashion becomes more difficult as design complexity increases. The requirements of current generation designs tax OPC engineers greater than ever before since the readiness of high-quality OPC models can delay new process qualifications or lead to respins, which add to the upward-spiraling costs of new reticle sets, extend time-to-market, and disappoint customers. In their efforts to extend the printability of new designs, OPC engineers generally focus on the data-to-wafer path, ignoring data-to-mask effects almost entirely. However, it is unknown whether reticle makers' disparate processes truly yield comparable reticles, even with identical tools. This approach raises the question of whether a single OPC model is applicable to all reticle vendors. LSI Logic has developed a methodology for quantifying vendor-to-vendor reticle manufacturing differences and adapting OPC models for use at several reticle vendors. This approach allows LSI Logic to easily adapt existing OPC models for use with several reticle vendors and obviates the generation of unnecessary models, allowing OPC engineers to focus their efforts on the most critical layers.