One of the major challenges of optical proximity correction (OPC) models is to maximize the coverage of real design
features using sampling pattern. Normally, OPC model building is based on 1-D and 2-D test patterns with
systematically changing pitches alignment with design rules. However, those features with different optical and
geometric properties will generate weak-points where OPC simulation cannot precisely predict resist contours on wafer
due to the nature of infinite IC designs and limited number of model test patterns. In this paper, optical property data of
real design features were collected from full chips and classified to compare with the same kind of data from OPC test
patterns. Therefore sample coverage could be visually mapped according to different optical properties. Design
features, which are out of OPC capability, were distinguished by their optical properties and marked as weak-points.
New patterns with similar optical properties would be added into model build site-list. Further, an alternative and more
efficient method was created in this paper to improve the treatment of issue features and remove weak-points without
rebuilding models. Since certain classification of optical properties will generate weak-points, an OPC-integrated repair
algorithm was developed and implemented to scan full chip for optical properties, locate those features and then
optimize OPC treatment or apply precise sizing on site. This is a named “in-situ” weak-point improvement flow which
includes issue feature definition, allocation in full chip and real-time improvement.
Implant layers must cover both logic and SRAM devices with good fidelity even if feature density and pitch differ very much. The coverage design rules of implant layers for SRAM and logic to active layer can vary. Lithography targeting could be problematic, since it may cause issues of either over exposure in logic area or under exposure in SRAM area. The rule-based (RB) re-targeting in the SRAM issue features is to compensate the under exposure in SRAM area. However, the global sizing in SRAM may introduce some bridge issues. Selective targeting and communicating with active layer is necessary. Another method is to achieve different mean-to-nominal (MTN) in some special areas during the reticle process. Such implant wafer issues can also be resolved during the lithography and mask optimized data preparing flow or named as lithography tolerance mask process correction (MPC).<p> </p> In this manuscript, this conventional issue will be demonstrated which is either over exposure in logic area or under exposure in bitcell area. The selective rule-based re-targeting concerning active layer will also be discussed, together with the improved wafer CDSEM data. The alternative method is to achieve different mean-to-nominal in different reticle areas which can be realized by lithography tolerance MPC during reticle process. The investigation of alternative methods will be presented, as well as the trade-off between them to improve the wafer uniformity and process margin of implant layers.