Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. Criteria specific to any lithographic process for the semiconductor industry include overlay, throughput and defectivity. The purpose of this paper is to describe the technology advancements made overlay, throughput and defectivity and to introduce the FPA-1200NZ2C cluster system designed for high volume manufacturing of semiconductor devices. in the reduction of particle adders in an imprint tool and introduce the new mask replication tool that will enable the fabrication of replica masks with added residual image placement errors suitable for memory devices with half pitches smaller than 15nm. Overlay results better than 5nm 3sigma have been demonstrated. To further enhance overlay, wafer chucks with improved flatness have been implemented to reduce distortion at the wafer edge. To address higher order corrections, a two part solution is discussed. An array of piezo actuators can be applied to enable linear corrections. Additional reductions in distortion can then be addressed by the local heating of a wafer field. The NZ2C cluster platform for high volume manufacturing is also discussed. System development continues this year with a target for introduction later in 2016. The first application is likely to be NAND Flash memory, and eventual use for DRAM and logic devices as both overlay and defectivity improve.
We shipped a small field exposure tool (SFET) to Selete (Semiconductor Leading Edge Technologies, Japanese
Consortium) in 2006. The SFET was founded for the purpose of EUVL mask and resist development. We have been
working on the exposure test and the tool evaluation in collaboration with Selete.
In the development of the SFET, We have experienced to connect two types of light source to the SFET, LPP light
source and DPP light source. And now we operate the SFET with DPP light source. On exchanging light source for DPP
light source from LPP light source, we planed to apply the new illuminator unit optimized for DPP light source. The new
illuminator unit of the SFET will improve dose uniformity on the imaging surface. We have installed the new illuminator
unit of the SFET at Selete in 2007, and evaluated the effects of dose uniformity.
In EUV lithography, the system performance reflects sensitively to the exposure results. We have been evaluating the
SFET quantitatively on mainly sensitive factors, in the system performance, to exposure result. We try to take a
correlation between the system performance and exposure results. In the system performance, the synchronization error
between the wafer and mask stages is one of the main factors to exposure sensitivity. We continue to evaluate the
relations between the system performance and the exposure results.