Si-Photonics is the technology in which data is transferred by photons (i. e. light). On a Photonic Integrated Circuit
(PIC), light is processed and routed on a chip by means of optical waveguides. The Si-Photonics waveguides
functionality is determined by its geometrical design which is commonly curved, skew and non-Manhattan. That is
why printing fidelity is very challenging on photonics patterns.
In this paper, we present two different Optical Proximity Correction (OPC) flows for Si-Photonics patterning. The
first flow is regular model based OPC and the second one is based on Inverse Lithography Technology (ILT). The
first OPC flow needs first to retarget the input layout while the ILT flow does support skew edges input by tool
design and does not need any retargeting step before OPC. We will compare these two flows on various Si-
Photonics waveguides from lithography quality, run time and MRC compliance of mask output. We will observe
that ILT flow gives the best Edge Placement Error (EPE) and the lowest ripples along the devices. The ILT flow
also takes into account the mask rules so that the generated mask is mask rule compliant (MRC). We will also
discuss the silicon wafer data where Si-Photonics devices are printed within the two different OPC flows at process
window conditions. Finally, for both OPC flows, we will present the total OPC run time which is acceptable in an
The 14nm node designs is getting more sophisticated, and printability issues become more critical which need more advanced techniques to fix. One of the most critical processes is the contact patterning due to the very aggressive design rules and the process window which becomes quickly limited. Despite the large number of RET applied, some hotspot configurations remain challenging. It becomes increasingly challenging to achieve sufficient process windows around the hot spots just using conventional process such as OPC and rule-based SRAF insertion. Although, it might be desirable to apply Inverse Lithography Technique (ILT) on all hot spots to guarantee ideal mask quality. However, because of the high number of hot spots to repair in the design, that solution might be much time consuming in term of OPC and mask processing.
In this paper we present a hybrid OPC solution based on local ILT usage around hot spots. It is named as Local Printability Enhancement (LPE) flow. First, conventional OPC and SRAF placement is applied on the whole design. Then, we apply LPE solution only on the remaining problematic hot spots of the design. The LPE flow also takes into account the mask rules so that it maintains the mask rule check (MRC) compliance through the borders of the repaired hot spot’s areas. We will demonstrate that the LPE flow enlarges the process window around hot spots and gives better lithography quality than baseline. The simulation results are confirmed on silicon wafer where all the hot spots are printed. We will demonstrate that LPE flow enlarges the depth of focus of the most challenging hot spot by 30nm compared to POR conventional solution. Because the proposed flow applies ILT solution on very local hot spot areas, the total OPC run time remains acceptable from manufacturing side.