EUV lithography is being prepared for insertion into the semiconductor production processes to continue the reduction of critical feature sizes at subsequent process nodes. To support that EUV wafer lithography development and production, the EUV photomask infrastructure similarly needs to be ready to support the shipment of EUV photomasks. EUV photomasks will require tighter process controls and tighter defect specifications to meet the requirements necessary for the wafer manufacturing insertion node. The novelty of the EUV lithography process combined with the high degree of complexity of the EUV photomask structure and process each contribute to the tightening of EUV photomask requirements, requiring accurate metrology to ensure fidelity to the photomask specifications. To fully address the industry requirements for EUV defectivity review and actinic mask qualification, ZEISS and the SUNY POLY SEMATECH EUVL Mask Infrastructure consortium have developed and commercialized the EUV aerial image metrology system, the AIMSTM EUV. The first commercial platform is already installed at a customer site and is available to support the EUV photomask production pipeline. This paper shows how the proven technology of the ZEISS aerial image system implemented into the AIMSTM EUV platform supports EUV photomask production in the back end of the line of Intel photomask manufacturing shop. Alongside with describing the essential development phases of the platform at customer site, examples of the reproducible measurement quality, as well as stability of the imaging fidelity of the system in production will be shown. In addition, the system output together with the experience on uptime and availability of the AIMSTM EUV platform in production is presented.
Electron beam resists are critical to photomask production and have significant impacts on advanced semiconductor manufacturing. In this paper, we’ll discuss current and future challenges in electron beam resist development. These materials face many of the same issues as EUV resists, especially in their tradeoffs between resolution, dose and LER. However, electron beam exposure creates unique complications associated with backscattered electrons and charging. We’ll investigate these effects and the requirements and challenges that result.
Mask patterning capability continues to be a key enabler for wafer patterning. Mask writer performance is critical to meet reticle resolution, critical dimension uniformity, registration, and throughput requirements. Technology trends indicate that mask requirements will require higher dose resists with more complex designs producing write time growth that significantly exceeds Moore’s law estimates. Sub 10 nm technology node requirements may exceed what is practically or economically achievable using conventional single beam writers. This is driving the need to explore alternative e-beam mask writer architectures for future nodes.
Several equipment suppliers are proposing new architectures for mask patterning. These approaches share the characteristic of some level of parallelism to solve the throughput challenge caused by increasing mask pattern complexity. Although parallelism is a proven approach in laser mask writers, it has not been integrated into an e-beam platform. All of the approaches for multibeam e-beam architectures have unique technical difficulties. In some cases, suppliers have produced proof of concept results to demonstrate the feasibility of their approach and address key technical risks. Although these results are encouraging, it is clear that they need more time and industry assistance to produce a commercially worthy mask writer.
Key drivers will be considered. Proposed evolutionary extensions of the current architecture will be evaluated. The need for revolutionary architectures to satisfy future mask patterning will be explored.
As photomask minimum feature size requirements continue to shrink, resist resolution limitations and their tradeoffs
with exposure dose are critical factors. Recently, nearly every node needs a new electron beam resist, customized for
exposure dose requirements while simultaneously meeting resolution specifications. Intel Mask Operations has an active
program focused on screening new electron beam resists and processes. We discuss the performance metrics we use to
evaluate materials and discuss the relative capabilities of the latest resists. We present fundamental resist metrics
(resolution, LER and dose) as well as manufacturing process sensitivities.
High resolution sub resolution assist features (SRAFs) are challenging to pattern, especially on photomasks with pattern
density variations and beam corrections. This paper presents analysis techniques of SRAF resist resolution performance
and manufacturing robustness. Electron beam proximity effects and their correction methods impact aerial image
quality. Resist resolution and LER depend strongly on the aerial image, and these effects will be looked at theoretically
and experimentally with CDSEM and reflected die-to-die inspection techniques. A quantitative understanding of
resolution process latitude is important in SRAF patterning, especially when one considers beam corrections that are
used to compensate for effects like electron fogging and etch loading.
Extreme Ultraviolet Lithography (EUVL) masks have residual stress induced by several thin films on low thermal
expansion material (LTEM) substrates. The stressed thin films finally result in convex out-of-plane displacement (OPD)
of several 100s of nm on the pattern side of the mask. Since EUVL masks are chucked on EUVL scanners differently
from on e-beam writer, the mask pattern placement errors (PPE) are necessary to be corrected for to reduce overlay
errors. In this paper, experimental results of pattern placement error correction using standard chrome on glass (COG)
plate will be discussed together with simulations. Excellent agreement with simple bending theory is obtained.
Suitability of the model to compensate for other EUVL-related PPEs due to mask non-flatness will be discussed.
Pixelated phase masks rendered from computational lithography techniques demand one generation-ahead mask
technology development. In this paper, we reveal the accomplishment of fabricating Cr-less, full field, defect-free
pixilated phase masks, including integration of tapeout, front-end patterning and backend defect inspection, repair,
disposition and clean. This work was part of a comprehensive program within Intel which demonstrated microprocessor
To pattern mask pixels with lateral sizes <100nm and vertical depth of 170nm, tapeout data management, ebeam write
time management, aggressive pattern resolution scaling, etch improvement, new tool insertion and process integration
were co-optimized to ensure good linearity of lateral, vertical dimensions and sidewall angle of glass pixels of arbitrary
pixelated layout, including singlets, doublets, triplets, touch-corners and larger scale features of structural tones
including pit/trench and pillar/mesa. The final residual systematic mask patterning imperfections were corrected and
integrated upstream in the optical model and design layout.
The volume of 100nm phase pixels on a full field reticle is on the order tera-scale magnitude. Multiple breakthroughs in
backend mask technology were required to achieve a defect free full field mask. Specifically, integration of aerial
image-based defect inspection, 3D optical model-based high resolution ebeam repair and disposition were introduced.
Significant reduction of pixel mask specific defect modes, such as electro static discharge and glass pattern collapse,
were executed to drive defect level down to single digit before attempt of repair. The defect printability and repair yield
were verified downstream through silicon wafer print test to validate defect free mask performance.
Aggressive 193nm optical lithography solutions have in turn led to increasingly complex model-based OPC methodologies. This complexity married with the inevitable march of Moore's Law has produced a figure count explosion at the mask writer level. Variable shaped beam equipment manufacturers have tried to mollify the impact of this figure count explosion on the write time by the introduction of new technologies such as increased beam current density, faster DAC amplifiers and more efficient stage algorithms. Despite these efforts, mask manufacturers continue to explore ways of increasing writer throughput and available capacity. This study models the impact of further improvements in beam current density and settling times. Furthermore, this model will be used to prescribe the necessary improvement rates needed to keep pace with the shot count trends extending beyond the 45nm node.
This paper includes an empirical determination of the relative CD error as a function of in-vacuum post exposure delay (PED). The effects of local pattern density and the impact of reticle proximity effect correction on the in-vacuum PED CD bias error are also considered. Results of dose compensation to improve CD uniformity on both artifact and production reticles are reviewed. The results show that by applying an exposure time dependent dose correction, the CD bias dependency upon in-vacuum PED is effectively compensated. In addition, the results show that dose compensation is effective at correcting for the in-vacuum PED dependency of local pattern density proximity errors. Finally, the paper concludes with a brief discussion of the relationship between existing reticle CD correction techniques for errors including electron beam fogging, etch loading, stable reticle process spatial CD non-uniformities and the new time dependent dose correction.
Alternating Phase Shift Mask (APSM) Technology has been developed and successfully implemented for the poly gate of 65nm node Logic application at Intel. This paper discusses the optimization of the mask design rules and fabrication process in order to enable high volume manufacturability. Intel's APSM technology is based on a dual sided trenched architecture. To meet the stringent OPC requirements associated with patterning of narrow gates required for the 65nm node, Chrome width between the Zero and Pi aperture need to be minimized. Additionally, APSM lithography has an inherently low MEEF that furthermore, drives a narrower Chrome line as compared to the Binary approach. The double sided trenched structure with narrow Chrome lines are mechanically vulnerable and prone to damage when exposed to conventional mask processing steps. Therefore, new processing approaches were developed to minimize the damage to the patterned mask features. For example, cleaning processes were optimized to minimize Chrome & quartz damage while retaining the cleaning effectiveness. In addition, mask design rules were developed which ensured manufacturability. The narrow Chrome regions between the zero and Pi apertures severely restrict the tolerance for the placement of the second level resists edges with respect to the first level. UV Laser Writer based resist patterning capability, capable of providing the required Overlay tolerance, was developed, An AIMS based methodology was used to optimize the undercut and minimize the aerial image CD difference between the Zero and Pi apertures.
A new chrome etch system was acquired and implemented to manufacture 65 nm node critical level masks. The etch performance of FEP 171, ZEP 7000, NEB 22, and REAP 200 resist systems in this new chrome etch system was evaluated. The critical dimension (CD) uniformity, etch bias, and etch linearity of this new etch system relative to the older generation etch system is presented. Implementation of the new etch system resulted in a 40-60 nm reduction in etch bias with no degrade in CD uniformity performance. In addition, it was found that the etch contribution to CD linearity was reduced by 50%. Detailed characterization of both macroloading and microloading etch effects was performed and showed substantial improvement relative to the previous generation etch system. The change in chrome etch rate as a function of etch area was reduced by 50%, improving mean to target CD performance on new designs. Implementation of the new etch system has enabled achievement of CD and defect density performance requirements for 65 nm node mask manufacturing. The results presented in this paper were collected during the process development phase and are not necessarily representative of the final optimized process.