Most current FPGA-based systems use a single static configuration per FPGA during applications. However, an attractive feature of the FPGA-based Reconfigurable System-on-Chip (rSoC) technology is the ability to dynamically change the configuration on the FPGA according to the requirements of the system, allowing the system to adapt to different environments and applications. In this paper, we describe a self-reconfiguring rSoC system which automatically and dynamically loads peripheral interface controllers, based on the peripherals connected to the system. There are two defined areas on one FPGA chip. A fixed area is used for the constant logic circuits (such as soft-core CPU) and partial reconfiguration (PR) areas are used for changeable peripheral interface controllers. The auto-configuration process involves three different steps: peripheral auto detection, loading of a peripheral hardware interface configuration, and loading of a peripheral software driver.
As part of the move to ubiquitous computing, sensor networks are an active topic for academic and commercial research. A variety of sensor network products and applications are appearing in the market. Environmental monitoring is a major application field for sensor networks, and the end users of such applications are generally average disciplinary scientists, i.e. environment researchers or ecologists. However, most current commercial sensor network products need extensive secondary development for adapting to different circumstances. This process, including replacing, adding, configuring and calibrating sensing elements, and configuring the network, is a difficult task for untrained end users. This paper introduces an ongoing project - Underwater Sensing Platform Network (USPN) - being developed at the University of Queensland which focuses on improvement of sensor network usability by providing a truly smart, plug-and-play sensing platform. Our approach is to investigate a novel architecture of a sensing node supporting different sensors and communication channels based on plug and play functionality to simplify the building and configuring process and to reduce the complexity, time and cost for deploying an environmental sensor network. The paper will describe both the system specification for the USPN plug-and-play marine sensor system, plus an initial system design.
Proc. SPIE. 6035, Microelectronics: Design, Technology, and Packaging II
KEYWORDS: Logic, Computing systems, Field programmable gate arrays, Telecommunications, Software development, Embedded systems, Operating systems, Data communications, Computer architecture, System on a chip
We propose an asymmetric multi-processor SoC architecture, featuring a master CPU running uClinux, and multiple loosely-coupled slave CPUs running real-time threads assigned by the master CPU. Real-time SoC architectures often demand a compromise between a generic platform for different applications, and application-specific customizations to achieve performance requirements. Our proposed architecture offers a generic platform running a conventional embedded operating system providing a traditional software-oriented development approach, while multiple slave CPUs act as a dedicated independent real-time threads execution unit running in parallel of master CPU to achieve performance requirements. In this paper, the architecture is described, including the application / threading development environment. The performance of the architecture with several standard benchmark routines is also analysed.
Proc. SPIE. 5274, Microelectronics: Design, Technology, and Packaging
KEYWORDS: Digital signal processing, Switching, Control systems, Telecommunications, Process control, Software development, Operating systems, Data communications, Computer architecture, Real-time computing
This paper introduces a computer architecture suitable for embedded real-time applications where low power consumption is a requirement. This is achieved through the use of a hybrid hardware-software system. A system architecture is proposed which allows for modules of a system to be implemented at run-time in either hardware or software. Implementation choices may be made dynamically based on the loading of the host microprocessor, in a multi-tasking environment. An approach to inter-module communication is described, along with how this is affected by dynamic configuration. Some research goals are identified, including investigating the effects on
real-time performance, power consumption and the design process involved in reconfigurable systems.
On-chip communication architectures can have a great influence on the speed and area of System-on-Chip designs, and this influence is expected to be even more pronounced on reconfigurable System-on-Chip (rSoC) designs. To date, little research has been conducted on the performance implications of different on-chip communication architectures for rSoC designs. This paper motivates the need for such research and analyses current and proposed interconnect technologies for rSoC design. The paper also describes work in progress on implementation of a simple serial bus and a packet-switched network, as well as a methodology for quantitatively evaluating the performance of these interconnection structures in comparison to conventional buses.
Reconfigurable System-on-Chip (rSoC) design is inherently a complex task with enormous freedom in design parameters such as processor, operating system, and backplane buses. Design efficiency can be improved by the use of an rSoC platform which constrains these choices, and allows new designs to leverage much of the expertise of previous designs. Egret is an rSoC prototyping platform being developed at the University of Queensland, Australia, and this paper explains and justifies the design decisions for the first version of Egret.
Initially, IP cores in Systems-on-Chip were interconnected through custom interface logic. The more recent use of standard on-chip buses has eased integration and eliminated inefficient glue logic, and hence boosted the production of IP functional cores. However, once an IP block is designed to target a particular on-chip bus standard, retargeting to a different bus is time-consuming and tedious. As new bus standards are introduced and different interconnection methods are proposed, this problem increases. Many solutions have been proposed, however these solutions either limit the IP block performance or are restricted to a particular platform. A new methodology is presented that can automate the connection of an IP block to a wide variety of interface architectures with low overhead through the use a special Interface Adaptor Logic layer.
Modern VLSI design is moving towards a System-on-Chip design paradigm, where chip design involves the integration of separate macrocells from different manufacturers. This paper explores the obstacles to adopting this same methodology for systems incorporating MEMS components. These obstacles include the technology specific nature of most MEMS devices, interference between MEMS sensors, and the limited electronics device density of mixed MEMS/Microelectronics technologies. It is conjectured that one fruitful avenue for further work is the development of MEMS interface circuits which can be incorporated into a single SoC along with other electronics macrocells, and which then connect to discrete MEMS sensor chips.
Many fast search block-matching motion estimation (BMME) algorithms have been developed in order to minimize the search positions and speed up the computation but they do not consider how they can be effectively implemented by hardware. In this paper, we propose a new regular fast search block-matching motion estimation algorithm named Two Step Search (2SS). The 2SS BMME will then be implemented by 8 Xilinx XC6216 fine-grain, sea-of-gate FPGA chips. The experimental and simulation results shows that it can have better algorithmic performance and can be implemented by FPGA chips very cost-effectively for video compression applications. Also, the 30 frames per second real time 2SS BMME video compression can be obtained by using eight Xilinx XC6216 FPGAs.
This paper explores the design and implementation of an adaptive Finite Impulse Response Filter on Reconfigurable Computing Technology (RCT). RCT deploys Field Programmable Gate Array technology as a flexible platform for implementing and improving digital systems design.
This paper presents how to implement the block-matching motion estimation algorithm efficiently by Field Programmable Gate Arrays (FPGAs) based Custom Computer Machine (CCM) for video compression. The SPACE2 Custom Computer board consists of up to eight Xilinx XC6216 fine- grain, sea-of-gate FPGA chips. The results show that two Xilinx XC6216 FPGA can perform at 960 MOPs, hence the real- time full-search motion estimation encoder can be easily implemented by our SPACE2 CCM system.
We present a technique for controlling the adaptive quantization process in an MPEG encoder, which improves upon the commonly used TM5 rate controller. The method combines both a spatial masking model and a technique for automatically determining the visually important areas in a scene. The spatial masking model has been designed with consideration of the structure of compressed natural images. It takes into account the different levels of distortion that are tolerable by viewers in different parts of a picture by segmenting the scene into flat, edge, and textured regions and quantizing these regions differently. The visually important scene areas are calculated using Importance Maps. These maps are generated by combining factors known to influence human visual attention and eye movements. Lower quantization is assigned to visually important regions, while areas classified as being of low visual importance are more harshly quantized. Results indicate a subjective improvement in picture quality, in comparison to the TM5 method. Less ringing occurs at edges, and the visually important areas of a picture are more accurately coded. This is particularly noticeable at low bit rates. The technique is computationally efficient and flexible, and can easily be extended to specific applications.