KEYWORDS: Logic, Logic devices, Chemical mechanical planarization, Multimedia, Very large scale integration, Signal processing, Digital signal processing, Video processing, Multiplexers, Electronics
This paper describes a new method for performing packed arithmetic on a prefix adder that enables sub-wordlength additions and subtractions to be performed in parallel on any prefix adder topology. A major benefit of the proposed technique is that the critical path length of the prefix carry tree is unaltered when measured as the number of complex CMOS logic gates. Moreover, there is no restriction on the prefix tree's cell topology and the adder is also capable of performing packed absolute difference and packed rounded average calculations.
In this paper we propose a thresholding technique for change detection in digital video. The technique assumes that the difference image generated from two frames of a video sequence has a trimodal Gaussian distribution and a computationally efficient fitting criterion is employed to find the best match between the data and model. Results show that the technique is capable of detecting true motion in very images.
KEYWORDS: Video coding, Wavelet transforms, Wavelets, Video, 3D video compression, 3D image processing, Digital filtering, Video compression, Electronics engineering, 3D imaging standards
In recent years 3D wavelet video coding has become a popular research area due to its low coding complexity. As the emerging MPEG-4 video compression standard places a strong emphasis on content base manipulation and compression, there is a need to implement the content coding feature within the 3D video coding algorithms. In this paper we propose a very simple algorithm to separate the foreground and background pixels for content based video coding. This algorithm exploits the 3D wavelet transform characteristics and only adds as small amount of overhead to the existing 3D video compression algorithms.
KEYWORDS: Error analysis, Digital filtering, Finite impulse response filters, Transistors, Pulse shaping, Quantization, Signal processing, Digital signal processing, Multiplexers, Clocks
A cascadable 10GOPS transversal filter chip has been designed and fabricated and can operate in 32-tap symmetric, 32-tap anti- symmetric or 16-tap non-symmetric modes. It has programmable tap weights and uses 16-bit signed arithmetic with radix-16 multipliers and 4 - 2 compressors to reduce the transistor count. The chip was fabricated in a 0.35 micrometer CMOS process, measures 3.1 X 4.4 mm and contains 310,000 transistors. The chip is pipelined and has a maximum clock rate of 200 MHz (200 MSa/s throughput). An error table compensator system using a lookup table has been built using the transversal filter programmed as a wideband differentiator with some additional on chip circuits including delays and an adder. An external memory stores the error table. The error table technique is capable of providing between 7 to 15 dB improvement in the dynamic range of typical 100 Ms/s A/D converters. An application to pulse shaping of high chip rate spread spectrum signals is also discussed.
This paper describes the design of very high speed optoelectronic analog digital converter based on a digital division algorithm called SRT division using n-i(MQW)-n self electro-optic effect device (SEED) technology. The proposed structure is a pipeline ADC. The SRT algorithm was chosen because it provides a redundancy per stage of the pipeline. The amount of redundancy is dependent on the radix of the SRT algorithm and the number set chosen. The relation between the SRT radix, number set and the division full range is given in this paper. Also a macro-model for the n- i(MQW)-n device was developed and used to simulate all the circuitry and algorithmic operations needed for the ADC. These included analog addition, analog subtraction and integer multiplication. Based on the developed macro-model and n-i(MQW)-n SEED circuit modules a basic unit of the algorithm ADC was designed.
KEYWORDS: Logic, Multiplexers, Transistors, Signal generators, Field effect transistors, Very large scale integration, Electronics engineering, Computer arithmetic, Signal processing, Gallium arsenide
This paper describes how a w-bit prefix-type carry-lookahead adder may be modified to yield more than one result per operation. The modified adder, called a 'flagged prefix adder', adds two 2's-complement numbers to give a sum S equals A + B but returns anyone of the following results: S; S + 1; -(S + 1); -(S + 2) as a function of a set of flag bits derived by the adder concurrently with the addition. Similarly, if the flagged prefix adder preforms the 2's-complement subtraction S equals A-B, the adder may return any one of: S, S- 1, -S, -(S + 1). Hence, the flagged prefix adder may be used to perform 'instant increment' or 'instant complement' operations. The extra logic required by the flagged prefix adder relative to the original prefix adder is 2w gates and w 2-to-1 multiplexers.
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