This paper presents an approach for the analysis and the experimental
evaluation of crosstalk effects due to current pulses drawn from
voltage supplies in mixed analog-digital CMOS integrated circuits. A
realistic model of bonding and package parasitics has been derived
to study digital switching noise injected through bonding
interconnections. Simulations results indicate that disturbances due
to switching currents in digital blocks propagate through the substrate and affect analog voltages, thus degrading circuit performance. Test structures have been integrated into a test chip mounted with different technologies, in order to compare the measurements on test chips. Measurements confirm simulation results.
Chip-on-board mounting technology has better performance with respect to chip-in-package, due to the reduction of parasitic elements.
KEYWORDS: Transmitters, Digital signal processing, Signal attenuation, Digital filtering, Signal processing, Antennas, CMOS technology, Electronic filtering, Frequency conversion, Filtering (signal processing)
The behavioral analysis and the design in a 0.13 μm CMOS technology of a digital interpolator filter for wireless applications are presented. The proposed block is designed to be embedded in the baseband part of a reconfigurable transmitter (WLAN 802.11a, UMTS) to operate as a sampling frequency boost between the digital signal processor (DSP) and the digital-to-analog converter (DAC). In recent trends the DAC of such transmitters usually operates at high conversion frequencies (to allow a relaxed implementation of the following analog reconstruction filter), while the DSP output flows
at low frequencies (typically Nyquist rate). Thus a block able to increase the digital data rate, like the one proposed, is needed before the DAC. For example, in the WLAN case, an interpolation factor of 4 has been used, allowing the digital data frequency to raise from 20 MHz to 80 MHz. Using a time-domain model of the TX chain, a behavioral analysis has been performed to determine the impact of the filter performance on the quality of the signal at the antenna. This study has led to the evaluation of the z-domain filter transfer function, together with the specifications concerning a finite precision implementation. A VHDL description has allowed an automatic synthesis of the circuit in a 0.13 μm CMOS technology
(with a supply voltage of 1.2 V). Post-synthesis simulations have confirmed the effectiveness of the proposed study.