Grayscale lithography is a well-known technique for three dimensional structuring of a photo sensitive material. The 3D structuring of the photoresist is performed by a spatially variable exposure. Pixelated grayscale mask structures are defined to achieve the desired 3D resist patterns by locally variable transmittance values. Within power semiconductor processing, grayscale techniques could beneficially be applied in different process steps. Several ideas come to mind for process simplification, alternative integration scheme and more, e.g. the realization of 3D resist patterns for implant applications in order to control the doping depth and profiles and their influence on device parameters. In order to make the grayscale process useful for manufacturing of semiconductor devices it is necessary to master and consider the inherent process variability. Lithographic simulation is used to optimize the sub-resolution photo-mask features and to predict the final resist shape and its variability. Device simulation for a DMOS device, used in our 130nm technology node, shows that the device performance would benefit from an attenuation of the implant dose in the center of the device, which could be achieved by creating a resist island with reduced resist thickness in the center of the drawn implant opening of the DMOS device. In order to achieve the desired target geometry of the implant resist mask, simulations with Sentaurus Lithography have been performed resulting in a suitable mask design and lithographic process. We will demonstrate the development of the grayscale litho-process based on the needs of an implant scheme that is going to be used for a DMOS device, with respect to process stability and achieved resist mask dimensions.
We have been utilizing rigorous simulation software in order to predict the alignment mark signal quality and mark contrast variation induced by processes changes reliably. We have run simulations in order to understand which parameters influence alignment mark quality most and to determine the important parameters that can be manipulated in order to improve it. Simulation of alignment signals (also referred to as waveforms) has been done for resist marks and etched marks, coated and uncoated, as well as in presence of increasing topography complexity. To validate simulation analysis, mark signal collection for different processes (and/or variations of those) and products has been carried out; cross sections have also been generated.
Grayscale lithography has become a common technique for three dimensional structuring of substrates. In order to make the process useful for manufacturing of semiconductor and in particular optoelectronic devices, high reproducible and uniform final film thicknesses are required. Simulations based on a calibrated resist model are used to predict customized process parameters from pixel layout to 3d substrate patterning. Multiple, arbitrary resist heights are reached by using i-line lithography. Scalable and uniform transfer of discrete step heights into oxide are realized by multiple alternating high selective resist and oxide (MASO) etch. Requirements and limitations of reliable 3D film thickness and uniformity control within a CMOS fabrication environment are being discussed.
A practical approach, adopting a clever litho trim, to spacer double patterning is investigated in detail. In order to produce quarter-pitch small lines of dense arrays (with pitch fragmentation techniques), state-of-the-art ArF photoresists can be used with a subsequent trim etch, to get the tiny line widths on desired target. Critical dimension (CD) control during the trim etch process plays a crucial role. Therefore, we investigated the application of a litho trim in order to reduce the trim etch close to zero bias. This approach has the further advantage to allow the printing of small spaces together with small lines, which reduces the k1 and, therefore, the theoretical resolution. Applying CD trim by litho “overexposure,” thin ArF bilayer system (silicon containing resist on spin-on carbon underlayer) showed basic suitability at k1=0.146 at half pitch of 3xnm with a sufficient process window and a good CD uniformity after litho and after etch. ArF single-layer resists suffer from pattern collapse and resist thickness loss at defocus. For spacer deposition directly on resist, the control of profiles and film thicknesses is shown to be difficult using single-layer resists and more likely to be achieved with bilayer resists. It is also shown that spacer-based double patterning can generate good CD uniformity by use of bilayer resist and litho trim, both with an a-Si carrier and bilayer resist carrier (underlayer).
To avoid expensive immersion lithography and to further use existing dry tools for critical contact layer lithography at
4Xnm DRAM nodes the application of altPSM is investigated and compared to attPSM. Simulations and experiments
with several test masks showed that by use of altPSM with suitable 0°/180° coloring and assist placement 30nm smaller
contacts can be resolved through pitch with sufficient process windows (PW). This holds for arrays of contacts with
variable lengths through short and long side pitches. A further benefit is the lower mask error enhancement factor
(MEEF). Nevertheless 3D mask errors (ME) consume benefits in the PW and the assist placement and coloring of the
main features (MF) put some constraints on the chip design. An altPSM compatible 4Xnm full-chip layout was realized
without loss of chip area. Mask making showed very convincing results with respect to CDU, etch depth uniformity and
defectiveness. The printed intra-field CD uniformity was comparable to attPSM despite the smaller target CDs. Room for
improvement is identified in OPC accuracy and in automatic assist placement and sizing.
KEYWORDS: Photomasks, Optical proximity correction, 3D modeling, Semiconducting wafers, Diffraction, Scattering, Near field, Lithographic illumination, Systems modeling, Near field optics
The perpetual shrinking in critical dimensions in semiconductor devices is driving the need for increased resolution in optical lithography. Increasing NA to gain resolution also increases Optical Proximity Correction (OPC) model complexity. Some optical effects which have been completely neglected in OPC modeling become important. Over the past few years, off-axis illumination has been widely used to improve the imaging process. OPC models which utilize such illumination still use the thin film mask approximation (Kirchhoff approach), during optical model generation, which utilizes a normal incidence. However, simulating a three dimensional mask near-field using an off-axis illumination requires OPC models to introduce oblique incidence. In addition, the use of higher NA systems introduces high obliquity field components that can no longer be assimilated as normal incident waves. The introduction of oblique incidence requires other effects, such as corner rounding of mask features, to be considered, that are seldom taken into account in OPC modeling. In this paper, the effects of oblique incidence and corner rounding of mask features on resist contours of 2D structures (i.e. line-ends and corners) are studied. Rigorous electromagnetic simulations are performed to investigate the scattering properties of various lithographic 32nm node mask structures. Simulations are conducted using a three dimensional phase shift mask topology and an off-axis illumination at high NA. Aerial images are calculated and compared with those obtained from a classical normal incidence illumination. The benefits of using an oblique incidence to improve hot-spot prediction will be discussed.
Patterning isolated trenches for bright field layers such as the active layer has always been difficult for lithographers.
This patterning is even more challenging for advanced technologies such as the 45-nm node where most of the process
optimization is done for minimum pitch dense lines.
Similar to the use of scattering-bars to assist isolated lines structures, we can use inverse Sub Resolution Assist Features
(SRAF) to assist the patterning of isolated trenches structures.
Full characterization studies on the C45 Active layer demonstrate the benefits and potential issues of this technique: Screen Inverse SRAF parameters (size, distance to main feature) utilizing optical simulation; Verify simulation predictions and ensure sufficient improvement in Depth of Focus and Exposure latitude with
silicon process window analysis; Define Inverse SRAF OPC generation script parameters and validate, with accurate on silicon, measurement
characterization of specific test patterns; Maskshop manufacturability through CD measurements and inspection capability.
Finally, initial silicon results from a 45nm mask are given with suggestions for additional optimization of inverse SRAF
for trenches.
Several qualification stages are required for new maskshop tools, first step is done by the maskshop internally. Taking
a new writer for example, the maskshop will review the basic factory and site acceptance tests, including CD
uniformity, CD linearity, local CD errors and registration errors. The second step is to have dedicated OPC (Optical
Proximity Correction) structures from the wafer fab. These dedicated OPC structures will be measured by the
maskshop to get a reticle CD metrology trend line.
With this trend line, we can:
- ensure the stability at reticle level of the maskshop processes
- put in place a matching procedure to guarantee the same OPC signature at reticle level in case of any
internal maskshop process change or new maskshop evaluation. Changes that require qualification could
be process changes for capacity reasons, like introducing a new writer or a new manufacturing line, or for
capability reasons, like a new process (new developer tool for example) introduction.
Most advanced levels will have dedicated OPC structures. Also dedicated maskshop processes will be monitored with
these specific OPC structures.
In this paper, we will follow in detail the different reticle CD measurements of dedicated OPC structures for the three
advanced logic levels of the 65nm node: poly level, contact level and metal level. The related maskshop's processes are
- for poly: eaPSM 193nm with a nega CAR (Chemically Amplified Resist) process for Clear Field L/S
(Lines & Space) reticles
- for contact: eaPSM 193nm with a posi CAR process for Dark Field Holes reticles
- for metal1: eaPSM 193nm with a posi CAR process for Dark Field L/S reticles.
For all these structures, CD linearity, CD through pitch, length effects, and pattern density effects will be monitored.
To average the metrology errors, the structures are placed twice on the reticle.
The first part of this paper will describe the different OPC structures. These OPC structures are close to the DRM
(Design Rule Manual) of the dedicated levels to be monitored.
The second part of the paper will describe the matching procedure to ensure the same OPC signature at reticle level.
We will give an example of an internal maskshop matching exercise, which could be needed when we switched from
an already qualified 50 KeV tool to a new 50 KeV tool.
The second example is the same matching exercise of our 65nm OPC structures, but with two different maskshops.
The last part of the paper will show first results on dedicated OPC structures for the 45nm node.
As semiconductor technology moves toward and beyond the 65 nm lithography node, the importance of Optical
Proximity Correction (OPC) models grows due to the lithographer's need to ensure high fidelity in the mask-
to-silicon transfer. This, in turn, causes OPC model complexity to increase as NA increases and minimum
feature size on the mask decreases. Subtle effects, that were considered insignificant, can no longer be ignored.
Depending on the imaging system, three dimensional mask effects need to be included in OPC modeling. These
effects can be used to improve model accuracy and to better predict the final process window. In this paper,
the effects of 3D mask topology on process window are studied using several 45 nm node mask structure types.
Simulations are conducted with and without a polarized illumination source. The benefits of using an advanced model algorithm, that comprehends 3D mask effects, will be discussed. To quantify the potential impact of this methodology, relative to current best known practices, all results are compared to those obtained from a model using a conventional thin film mask.
Today novel RET solutions are gaining more and more attention from the lithography community that is facing new challenges in attempting to meet the new requirement of the SIA roadmap. Immersion, high
NA, polarization, and mask topography, are becoming common place terminology as lithographers continue to explore these areas.
Here with, we compare a traditional 6% MoSi based EAPSM reticle and a high transmission solution made of a SiON/Cr film stack. Insights into the manufacturability of high transmission material are
provided. Test patterns have been analyzed to determine the overall impact of imaging performance when used with immersion scanners and polarized light. Some wafer results provide reliability of simulations, which are used to make further investigation on polarization and immersion effects.
Phase-shift mask (PSM) technology in combination with 193nm illumination remains a viable option for high
contrast imaging towards 45nm half-pitch applications. The advent of hyper NA (immersion) lithography increases the
imaging sensitivity towards the photomask properties, such as mask-induced polarization. In addition, the use of PSM
technology implies taking into account the inherent photomask topography effects for a balanced through pitch imaging. A
good quartz etch depth control of +/-1o through pitch is required for optimized wafer imaging [1]. Therefore, a new PSM
material stack was proposed based on a transparent etch stop layer (TESL) in order to meet the stringent phase depth
requirements beyond 65nm half-pitch [2]. This extra layer allows over-etching of the quartz, resulting in a good etch depth
linearity and uniformity.
This study examines the manufacturability and printability of TESL-based masks. We examine the effect of an
improved quartz etch depth linearity on the through-pitch process windows for a TESL-based alternating aperture (AA)PSM.
Moreover, due to the different stack of photomask material compared to a classical photomask blank, the impact on
printability is investigated by simulations, AIMS and wafer imaging. The image imbalance compensation by trench biasing
needs to be optimized for through-pitch process windows.
The actual depth and line width of the structures is systematically probed within the photomask field. Based
on photomask metrology data, rigorous electro-magnetic field simulations are compared to wafer prints, obtained on an
ASML XT1250Di ArF immersion scanner working with a 0.85NA projection lens and to AIMS results from Zeiss
AIMS fab 193i.
Furthermore, feature sizes on the order of the lithography wavelength induce photomask polarization effects in the
imaging path [3]. The degree of polarization is compared to the polarization behavior of a conventional PSM.
In summary, this study assesses the capability of TESL PSM towards the 65nm node through-pitch imaging.
Today novel RET solutions are gaining more and more attention from the lithography community that is facing new challenges in attempting to meet the new requirement of the SIA roadmap. Immersion, high NA, polarization, and mask topography, are becoming common place terminology as lithographers continue to explore these areas. Here with, we compare a traditional 6% MoSi based EAPSM reticle and a high transmission solution made of a SiON/Cr film stack. Insights into the manufacturability of high transmission material are provided. Test patterns have been analyzed to determine the overall impact of imaging performance when used with immersion scanners and polarized light. Some wafer results provide reliability of simulations, which are used to make further investigation on polarization and immersion effects.
We explore technical and practical issues to apply EAPSM technology with high transmission into ArF lithography. This technique needs to be reviewed in the standpoint of process and device fabrication using short wavelength, high NA, OAI and OPC technology. In this paper, we analyze optical characteristics of multi-stacked film that composed of phase material like MoSi, Cr-SiON, Cr-SiO2, and Ta-SiO2. Three-dimensional analyses of film structure are to consider intensity variations and optical influence by n &k value, thickness and polarization light. The comparison will be focused on optimization or determination of each high T materials. Moreover, we specify CD impacts of mask CD error, variations of phase and transmission for various pattern size, and 3D structure. Polarization effect in this structure and high NA condition will be also interesting part to be studied impacts on process.
In the device application of technology, we consider overall process margin to satisfy cell & periphery design rule and OPC treatment to improve process windows. Optimum SRAF design and tri-tone mask technology will be key issue to improve DOF margin of specific design rule in OPC treatment. For 65nm technology or less, intensity formation distributed on mask affects CD and process margin directly on wafer patterning process. High transmission EAPSM will have specifically differences with 6% EAPSM in OPC treatment and it will be required new OPC rule in ArF lithography. Using simulation and experiment, we find high transmission EAPSM has advantages in device manufacturing and approach technical issue to be solved in material, process and device application. This technique shows to improve exposure latitude & DOF margin, and to reduce MEEF in process. Finally it will be good candidate to satisfy lithography requirement of 65nm and 45nm node.
Today novel RET solutions are gaining more and more attention from the lithography community that is facing new challenges in attempting to meet the new requirement of the SIA roadmap. Immersion, high NA, polarization, and mask topography, are becoming common place terminology as lithographers continue to explore these areas. Here with, we compare a traditional 6% MoSi based EAPSM reticle and a high transmission solution made of a SiON/Cr film stack. Insights into the manufacturability of high transmission material are provided. Test patterns have been analyzed to determine the overall impact of imaging performance when used with immersion scanners and polarized light. Some wafer results provide reliability of simulations, which are used to make further investigation on polarization and immersion effects.
Today the industry is filled with intensity-balanced c:PSM and much more focus is being placed on innovative approaches such as CPL (and in conjunction with IML for Contacts) and tunable transmission embedded attenuating phase shift mask (TT-EAPSM). Each approach has its own merits and demerits depending on the manufacturing strategy and lithography performance required. Currently the only commercially available photomask blanks are different chrome thickness binary and 6% attenuating blanks using molybdenum-silicide, making the accessibility to alternate transmissions much more challenging. This paper investigates the mask manufacturability of a tunable transmission embedded attenuating phase shift mask. New film materials that are used in the mask blank manufacture are modeled, deposited and characterized to determine its ability to meet performance requirements. Sputtering models, by rate and gas component, determines film stacks with tunable transmissions and thicknesses. Chemical durability, etch selectivity and thickness are a few parameters of the films that have been characterized to enhance the manufacturability and process reliability of the masks. Lithography simulation models using measured optical properties were developed and test masks that include actual device designs were fabricated. Analysis of CD variation, pattern fidelity and process margin was performed using 3D mask simulation to understand the impact on 65nm design rules. Feasibility and performance of tunable transmission photomasks for use in design and lithography are verified. Moreover, the mask manufacturability and lithography performance is compared to other enhancement techniques and their merits presented.
A chrome-less phase-shift mask for the 70nm technology was designed and manufactured. The mask contains “lines and spaces” including programmed defects. Each defect was characterized with respect to the critical dimension (CD) variation on wafer, defect size, aerial image deviation, as well as inspection capture rate. It was found that defects with an AIMS intensity deviation of above 9 % are to be considered critical. The corresponding critical defect size is dependent on the defect type. All lithographically significant mask defects were found reliably using a KLA 576 inspection tool.
The lithographic potential of various mask types for the printing of 65nm features has been investigated by simulation and experimentation. As key parameters process window, mask error enhancement factor, balancing performance, and phase and CD error susceptibility have been analyzed. Alternating chromeless phase-shifting masks (PSM) show the smallest mask error enhancement factor (MEEF), but the largest phase and CD error sensitivity. Alternating PSM have a larger MEEF but require less tight mask specifications. Double edge chromeless PSM combine small MEEF value with relaxed phase and CD control specifications when an appropriate illumination is chosen. Good intra-field CD control and sufficient large process window for 65nm pattern can be obtained for this mask type. The impact of aberrations and pupil imperfections on the CD control has been investigated. The mask processes will be discussed and mask performance data introduced.
With alternating phase shift masks (altPSM) an enhancement technique is available to realize smaller design rules. Meanwhile the basic production process for this mask type is well known and established for 193nm technology development. The qualification of the masks is now in the focus of development work. Sensitive defect inspection is essential for the qualification of altPSMs. In addition accurate phase and transmission balancing measurement technique has to be applied. In this paper we are presenting a detailed defect printability study for sub-100nm feature size technology at 193nm wavelength. Programmed quartz defects with different shapes and sizes were designed. They were implemented in a lines/spaces altPSM design. The processed quartz defects were characterized with a scanning electron microscope and an arial imaging microscope system. The printing behavior of the defects was analyzed after wafer exposures. In addition the required sensitivity for the altPSM inspection was evaluated. Finally the inspection sensitivity was characterized and optimized with programmed and production like defects.
The lithographic potential of alternating PSM for sub-100nm gate patterning have been evaluated in comparison to alternative techniques. The status of the key elements of the full level alternating PSM approach including design conversion, optical proximity correction, mask making, double exposure and phase-shifting mask imaging will be demonstrated for a 256MDRAM device. Experimental data describing the phase-shifting mask quality, the lithographic process windows and the CD control obtained for alternating PSM in full level and array only approach will be presented.
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