The testing and evaluation of a low cost system capable of estimating the position of a moving target within an extendible indoor area with low error is presented. Based on a recently developed system architecture, which makes use of a noise-sensitive indoor localization system made up of ir sensors, the position estimation error is based on comparing the number of the digital ir patterns received at the moving target with the expected one. To overcome the problem of instant noise that appears despite the effective system shielding, we employ a number of rules that take into consideration the previous position estimations. These rules are based on the fact that the speed of the target is always limited and its track is smooth most of the time. The test for the rules was made by running a series of experiments on the sensors system, and as a result, we verified that the maximum absolute error in the experimental results is approximately equal to the grid node distance. Moreover, the noise restrictions of the system were tested and recognized, allowing direct measurement of relevant parameters.
Design and construction of new sub-micron MOSFETs with alternative gate dielectrics has emerged as a new technology for use in high-performance logic or low power memory circuits. The modelling of the new devices needs to take into account the effects that the new dielectrics have on the MOS device performance. In this paper, we examine such effects in terms of both capacitance and leakage current effects. First, we investigate the role of the parasitic capacitances appearing at the MOS device due to either material related processes or metallization. These capacitances are modelled accordingly in order to derive the device characteristics. Then, leakage currents are taken into account and the whole device is simulated using a 90 nm technology based on the BSIM4 model equations, suitably modified to account for these effects. The application of such devices on memory circuits is examined in order to take into account device parameters such as the threshold voltage, ouput currents and timing. As a result, the design of an embedded DRAM based on the MOSFETs with the alternative gate dielectrics is presented and analysed. The single MOSFET behaviour and subsequently the DRAM circuit performance are presented and the relevant characteristics are derived. As a result, the simulation revealed low output currents for the MOSFETs and high refresh rates for the DRAM circuits. Deviations from the ideal case are examined and solutions and further work are proposed.