Galileo Galilei once quoted: “Measure what is measurable, and make measurable what is not so”. In silicon manufacturing R&D phase, it often happens that engineers would like to access some parameter values that are not easy, even impossible to measure. When looking at a CDSEM image, the parameters of interest seem easy to extract but in practice getting access to them in a robust and reliable way is not always simple. Developing a contour-based metrology tool coupling robust contour extraction with a comprehensive contour metrology environment could help to bridge this gap. In previous works, it has been shown that SEM images contain significant amounts of information that can be extracted and analyzed using efficient contour extraction and analysis toolboxes [1, 2]. Also, the concept of implementing remote contour-based metrology has been introduced. The present work continues to unveil what can be achieved with such solutions. For that, the example of implant layers’ process assumption will be explored. During this process step, counter doping problems can occur for example when the distance between layers deviates from nominal. Therefore, it is crucial for design rule control to measure some critical dimensions such as minimum distance between layers, corner rounding, slope, etc. However, given the characteristics of the different structures in the images, which may come from different layers and/or processes steps, the measurements are not straightforward to extract with standard CDSEM metrology algorithms. Moreover, recipes are complex to setup, measurements by themselves are not very stable, and usually an indirect determination of the key figure is performed. In this paper, we will show that multilayer contour-based metrology, mixing image contour and GDS layout, allows to overcome the previously mentioned difficulties, as well as to generate measurements that are not possible to be performed by using standard algorithms.
Multiple electron beam direct write lithography is an emerging technology promising to address new markets, such as truly unique chips for security applications. The tool under consideration, the Mapper FLX-1200, exposes long 2.2 μm-wide zones called stripes by groups of 49 beams. The critical dimensions inside and the registration errors between the stripes, called stitching, are controlled by internal tool metrology. Additionally, there is great need for on-wafer metrology of critical dimension and stitching to monitor Mapper tool performance and validate the internal metrology.
Optical Critical Dimension (OCD) metrology is a workhorse technique for various semiconductor manufacturing tools, such as deposition, etching, chemical-mechanical polishing and lithography machines. Previous works have shown the feasibility to measure the critical dimension of non-uniform targets by introducing an effective CD and shown that the non-uniformity can be quantified by a machine learning approach. This paper seeks to extend the previous work and presents a preliminary feasibility study to monitor stitching errors by measuring on a scatterometry tool with multiple optical channels.
A wafer with OCD targets that mimic the various lithographic errors typical to the Mapper technology was created by variable shaped beam (VSB) e-beam lithography. The lithography process has been carefully tuned to minimize optically active systematic errors such as critical dimension gradients. The OCD targets contain horizontal and vertical gratings with a pitch of 100 nm and a nominal CD of 50 nm, and contain various stitching error types such as displacement in X, Y and diagonal gratings.
Sensitivity to all stitching types has been shown. The DX targets showed non-linearity with respect to error size and typically were a factor of 3 less sensitive than the promising performance of DY targets. A similar performance difference has seen in nominally identical diagonal gratings exposed with vertical and horizontal lines, suggesting that OCD metrology for DX cannot be fully characterized due to lithography errors in gratings with vertical lines.
Future of logic silicon extension lies at the heart of gate all around developments (1). Due to the increasing limitations in further FinFET flow extension, teams around the globe are researching with vertical and horizontal nanowires flavors. Horizontal NW are of great interest due to their integration similarity to the existing FinFET integration flow (2). This in turn allows to extend the usage of existing process and metrology platforms, and reduce the cost of shifting to a new technology. Even though the integration changes seem limited, it springs many new obstacle for fab metrology. New parameters of interest take place, and the metrology capability needs to reach higher performance, and develop new solution methods (3,4).
The current paper will focus on one of the new rising metrology challenges, which exist at the nanowire release process step. The nanowire release step, a SiGe dummy layer is being removed by dry etching, to leave behind the active Silicon nanowires, for nfet device. A detailed metrology of these nanowire profile and thickness is required to verify the device can perform to the expected specifications. To examine the scatterometry performance at this application, a specific design of experiment was set, at multiple process step. at fin formation we begin with split condition, on the silicon-silicon germanium (Si-SiGe) multi layer deposition, where SiGe , are being varied between wafers, by increasing the SiGe layer thickness, thus different amount of SiGe material will be released (figure 1a). Scatterometry and X-ray reflectivity (XRR) are verifying this split condition (figure 1b). We continue with additional split condition for the fin reveal, allowing the lower SiGe layer to be more or less revealed to the SiGe release etching step (figure 2a). To confirm the fin height for the different splits condition we use atomic force microscope (AFM), and scatterometry (figure 2b). the last process DoE we report is the etching method in which the SiGe is released. The two etch methods, we address in this paper, provides different nanowire profile (figure 3), a circular or rectangular shapes, respectively. The last part of this paper will highlight how scatterometry nanowire profile accuracy, at the SiGe release step, is improved by incorporating the complete GAA steps scatterometry solutions, and the combination of Transmission electron microscopy (TEM) rich sampling.
The evaluation of scatterometry for monitoring intended variations in innovative scatterometry targets that mimic nonuniformities potentially caused by multibeam Maskless Lithography (MEB-ML2) is presented. Specialized scatterometry targets consisting of lines and spaces were produced that have portions exposed using the nominal, or POR (Process of Record), dose, and portions exposed with a slightly different dose. These exposure plans created targets with different line CDs (critical dimensions). Multiple target designs were implement, each with a different combination of magnitude of CD shift and size of the region containing lines with a shifted CD. The scatterometry, or OCD (Optical Critical Dimension), spectra show clear shifts caused by the regions with shifted CD, and trends of the scatterometry results match well with trends of the estimated CD as well as the trends produced by measurements using a critical dimension scanning electron microscope (CD-SEM) system. Finally, the OCD results are correlated to the CD-SEM measurements. Taking into account resist morphology variations across the wafer, correlations between OCD and CD-SEM of the weighted average CD across the various targets are shown to be very good. Correlations are done using the rigorous TMU analysis methodology. Due to the different targeted CD values within each scatterometry structure, a new methodology for estimating the error of the CD-SEM measurements for nominally non-uniform targets is presented.
Introduction of new material stacks, more sophisticated design rules and complex 3D architectures in
semiconductor technology has led to major metrology challenges by posing stringent measurement
precision and accuracy requirements for various critical dimensions (CD), feature shape and profile.
Current CD metrology techniques being used in R&D and production such as CD-SEM, Scatterometry,
CD-AFM, TEM have their inherent limitations that must be overcome to fulfil advanced roadmap
requirements. The approach of hybrid automated CD metrology seems necessary. Using multiple tools in
unison is an adequate solution when adding their respective strengths to overcome individual limitations.
Such solution should give the industry a better metrology solution than the conventional approach.
In this work, we will present and discuss a new methodology of CD metrology so-called hybrid CD
metrology that mixes CD data coming from different techniques. In parallel to this hybrid metrology
approach, we must address individual technique enhancement. Subsequently, scanning techniques
enhancement will be presented (CD-SEM and CD-AFM) through contour metrology parameter which
should become a pedestal feature for 1x node production. Finally, we will discuss the potential directions
of a hybrid metrology engine as a generic tool compatible with any kind of CD metrology techniques.
Introduction of new material stacks, more sophisticated design rules and complex 3D architectures in
semiconductor technology has led to major metrology challenges by posing stringent measurement precision
and accuracy requirements for various critical dimensions (CD), feature shape and profile. Current CD
metrology techniques being used in development and production such as CD-SEM, scatterometry and CDAFM,
individually have intrinsic limitations that must be overcome. The approach of hybrid automated
metrology seems necessary. Using multiple tools in unison is an adequate solution when adding their
respective strengths to overcome individual limitations. Such solution will give the industry a better
metrology solution than the conventional approach. Nevertheless, this is not enough since the industry is
requested for 2D and 3D profiles information. Indeed, CD, height and/or Sidewall angle are information
which is limited for future nodes production. Full profile information is necessary.
In this paper, the first part will be dedicated to the introduction of contour object as a new standard for the
semiconductor industry. This metric will take into account all pattern's profile information in order to
overcome the limitations of simple CD and/or SWA information. The second part will present and discuss
results concerning data fusion and its application to hybrid metrology. We will illustrate hybrid metrology
with an application to CD-SEM enhancement with a reference technique such as the AFM3D or TEM
technology. We will show that it could be possible to improve RMS error of CD-SEM by a factor of 78%. We
think that such trend can be extended to all microelectronic levels in IC manufacturing and subsequently
significantly reduce cycle time and improve production yield through easier hotspot detection.