We develop a new double exposure Moire method for an optical registration metrology system in photolithography. Our method enables us to achieve at least a factor of 10 improvements in precise displacement metrology using a conventional optical sensor. We utilize a new registration mark printed to the photoresist on a bare silicon wafer using a double exposure of the gratings. The mark consists of two types of Moire with opposite phases. The two types of Moire are oriented in alternate directions. Displacement is measured from the distance between the positions of the two types of Moire in analogy with the conventional registration method. This concept is called alternating direction Moire. Performance is experimentally confirmed using an i-line wafer exposure apparatus. Precision is improved by up to 32 times as compared with the conventional method and can be applied to other Moire metrologies.
The problem of the alignment tree for double patterning (DP) is presented. When the 2nd DP exposure is aligned to the
underlying zero layer, the space CD uniformity is shown to be well outside the budget for the 32 nm HP node. Aligning
the 2nd DP layer to the zero layer gives better overlay results, but aligning the 2nd DP pattern to the 1st DP pattern gives
results well within the overlay requirements for the 32 nm HP. Aligning the 2nd DP layer to the 1st DP layer is
recommended to give the best CD uniformity and overlay results. Experimental results show, qualitatively, the CD
uniformity is significantly worse when the 2nd pattern is aligned to the zero layer, but the overlay for both alignment trees
could be corrected to roughly the same levels. The raw overlay data shows a significantly different signature for the two
alignment trees, possibly caused by alignment mark signal differences between the marks on the zero and 1st layers, or
distortion of the zero layer after the first etch. The requirements for a DP exposure tool were reviewed and can be
summarized as improved dose control, improved overlay performance, and significantly higher throughput.
Double patterning (DP) is today the main solution to extend immersion lithography to the 32 nm node and beyond. Pitch
splitting process with hardmask transfer and spacer process have been developed at CEA-LETI-Minatec. This paper
focuses on experimental data using dry ArF lithography with a k1 factor of 0.20 ; the relative impact of each DP step on
overlay and CD uniformity budgets is analyzed. In addition, topography issues related to the presence of the patterned
hard mask layer during the second imaging step is also investigated. Tool-to-itself overlay, image placement on the
reticle and wafer deformation induced by this DP process are evaluated experimentally and resulting errors on CD
budget have been determined. CD uniformity error model developed by Nikon describing the relationship between CD
and overlay in different DP processes is validated experimentally.
Double patterning (DP) has now become a fixture on the development roadmaps of many device manufacturers for half pitches of 32 nm and beyond. Depending on the device feature, different types of DP and double exposure (DE) are being considered. This paper focuses on the requirements of the most complex forms of DP, pitch-splitting (where line density is doubled through two exposures) and spacer processes (where a deposition process is used to achieve the final pattern). Budgets for critical dimension uniformity and overlay are presented along with tool and process requirements to achieve these budgets. Experimental results showing 45-nm lines and spaces using dry ArF lithography with a k1 factor of 0.20 are presented to highlight some of the challenges. Finally, alternatives to DP are presented.
Double patterning is recognized as the best candidate for 32 nm half-pitch lithography. Currently pitch splitting processes are being considered for logic processes and spacer processes are being considered for memory. In pitch splitting, errors in overlay between the first and second exposure become CD errors on the final pattern. For this reason, overlay requirements are severe for pitch splitting double patterning. Revised CD and overlay budgets are presented, as well as technical requirements to satisfy these budgets. Spacer processes do not have similar restrictions on overlay, so they can be achieved using current immersion tools. Exposure tool requirements for double patterning are discussed and modifications to current platforms are described.
Nikon's production immersion scanners, including the NSR-S609B and the NSR-S610C, have now been in the field for
over 2 years. With these tools, 55 nm NAND Flash processes became the first immersion production chips in the world,
and 45 nm NAND Flash process development and early production has begun. Several logic processes have also been
developed on these tools. This paper discusses the technical features of Nikon's immersion tools, and their results in
Double patterning (DP) has now become a fixture on the development roadmaps of many device manufacturers for half
pitches of 32 nm and beyond. Depending on the device feature, different types of DP and double exposure (DE) are
being considered. This paper focuses on the requirements of the most complex forms of DP, pitch splitting, where line
density is doubled through two exposures, and sidewall processes, where a deposition process is used to achieve the final
pattern. Budgets for CD uniformity and overlay are presented along with tool and process requirements to achieve these
budgets. Experimental results showing 45 nm lines and spaces using dry ArF lithography with a k1 factor of 0.20 are
presented to highlight some of the challenges. Finally, alternatives to double patterning are presented.
Overlay accuracy is a key issue in the semiconductor manufacturing process. To achieve overlay requirements, we developed compensation functions, i.e. Enhanced Global Alignment (EGA), Super Distortion Matching (SDM), and Grid Compensation for Matching (GCM). These functions are capable to reduce all the components except local linear components caused by a wafer global deformation. In this paper we introduce a novel correction framework which includes new compensation function called Shot Correction by Grid Parameter; thereby enabling further enhancements to overlay. Using this novel framework, we show both simulation and experimental data demonstrating improved overlay accuracy.
To maintain the best imaging performance of current high NA DUV scanners, in-situ aberration measurement is becoming more important than ever. In this paper, we present an aerial image based aberration measurement technique that can measure the aberrations up to 37<sup>th</sup> Zernike polynomial term. Our aberration measurement technique uses aerial image sensor (AIS) on DUV scanners. AIS is a slit scanning type aerial image sensor that can capture the one-dimensional intensity distribution of aerial images. Unlike previous photo resist image based aberration measurement technique, presented technique does not require the three-beam interference condition or the two-beam interference condition because it utilizes the image intensity information. This can eliminates the geometrical restriction in determination of the pupil sampling points. Thus, we made optimization of pupil sampling so that it can minimize the random error propagation in each Zernike coefficients. This optimization was done on a trial and error basis and we observed that the random error propagation significantly depended on pupil sampling plan. The measured aberration was correlated to the programmed aberration induced by lens element displacement. Also the measurement repeatability was evaluated and confirmed. The overall performance of this aberration measurement technique is found to be appropriate for in-situ aberration monitor of current high NA scanners.
Various alignment methods for a semiconductor exposure tool have been proposed and developed. Especially, the TTR (through the reticle) alignment technique has been expected as the ideal system since the direct measure between a reticle and a wafer through the projection lens has no baseline error. However, it requires that an alignment illumination be a single wavelength of the exposure light because of the chromatic aberration of the projection lens. The strong absorption by the resist and the BARC (bottom anti reflective coating) weakens the alignment signal intensity, and the interference fringe in the resist by the single wavelength sacrifices the precise position detection. Such difficulty in signal detection has blocked the TTR system from becoming realized. We tried to address this problem by peeling the resist and BARC on alignment marks. To peel the resist and BARC, we performed elective ablation using a laser ablation method with the Q-switch Nd YAG laser. The laser-ablated alignment marks on some process wafers were measured by the TTR alignment system. The signal waves with enough contrast were measured over all wafers and the satisfied alignment accuracy was examined.
Outliers in measurement often interfere with alignment. They are caused by sudden damages in the alignment mark, and existence of particles, resist damages and so on. In a conventional way to identify outliers, the observations that have larger residual than previously determined threshold are identified as outlier. It works well only with the operator’s labor of adjusting the threshold according to the deviation of <i>ordinaries</i> (non-outliers). However, labor is a problem especially in Small-Quantity Large-Variation fabrication such as for ASIC, System-LSI and so on. A novel method for elimination of the labor has been developed. It utilizes normal mixture models whose number of components is determined based on the Maximum Penalized Likelihood (MPL) method. It can be regarded as an identification method that determines threshold adaptively using <i>ordinaries’ </i>deviation. Simulation results show that the penalty coefficient, the only parameter of the method, can be a constant in the variation of <i>ordinarie's</i> deviation. It also shows that in the absence of outliers, the accuracy of the method is comparable with the maximum likelihood estimation that is commonly considered to be the best method when the observations follow the normal distribution. The method performs better than conventional ones when there are a sufficient number of observations (no less than ten) in the standard Enhanced Global Alignment (EGA). Superiority of the adaptive method is dependent upon the probability of outlier occurrence, variation of the <i>situation</i>, the number of observations and the complexity of the model fitted to the observations.
We have developed a new mask patterning system, which can fabricate 130nm generation masks by means of a stitching exposure technique. We call this system the Photomask Repeater (PR)1,23,4. The PR is a 5x i-line stepper modified for mask manufacturing with a field size of 22x22mm in a single exposure. However, the device size on a 4x mask is larger than 22x22mm. Furthermore, excellent mask CD uniformity is required. For this purpose the exposure field size was extended with the use of “seamless stitching technology”. This is clearly the key to obtaining a practical, accurate mask patterning system. Results have been achieved on masks with this system showing CD variation of less than +/- 7nm at a stitching area by means of a “gradation filter”. Moreover, overall CD uniformity is 10.36nm (3?), while image placement accuracy is 17.8nm (3?) and 2nd alignment accuracy is 24.1nm (3?). PR is an attractive system for System on Chip mask manufacturing, and is also effective in reducing Turn Around Time.
A Device mask of 180nm generation was fabricated by Photomask Repeater system and the performance of it proved to be high by the results of fabricated mask. Great margins between the results of the fabricated mask and specifications suggest that lower graded masks can be used as master masks. From this point of view, error budgets were estimated about CD uniformity and pattern placement. The required specifications for master mask were estimated for 180nm and 130nm lithography. In CD uniformity the specification is 50nm(3?) for 180nm and 30nm(3?) for 130nm lithography. In pattern placement the specification is 75nm(3?) for 180nm and 50nm(3?) for 130nm lithography. In defect size the specification is lOOOnm for 180nm and 900nm for 130nm lithography. The requirements of master mask are rather rough even for 130nm lithography and enough realistic.
We have developed a new reticle exposure system, which can fabricate 150nm generation masks by means of a stitching exposure technique. We call this exposure system the Photomask Repeater, or high accuracy repeater (HR). HR is a modified i-line stepper for mask manufacturing with a field size of 22 by 22 mm in a single exposure. However, the device size on a 4x mask is larger than 22 by 22 mm. Furthermore the improvement in mask CD uniformity is required. For this purpose the exposure field size was extended with the use of 'seamless stitching technology'. This is the key to obtaining a feasible exposure system with the use of this method. Results have been achieved with this system showing CD variation of less than +/- 5 nm across a 1D seam band by means of a 'gradation filter'. Moreover, overall Cd uniformity is less than 13nm, while image placement accuracy is less than 24nm. HR is an attractive system for SoC mask manufacturing, and is also effective in reducing TAT.
Proc. SPIE. 4066, Photomask and Next-Generation Lithography Mask Technology VII
KEYWORDS: Lithography, Kinematics, Scanning electron microscopy, Printing, Photomasks, Optical proximity correction, Critical dimension metrology, Semiconducting wafers, System on a chip, Process engineering
New pattern generation system, Photomask Repeater, based on i-line stepper has been developed. This system can transfer device patterns from master masks onto a photomask plate with 22mm field size. To print a chip larger than the 22mm field, stitching technology has been developed. Critical dimension error in the region where fields are stitched is the key issue of this technology. Quantification of critical dimension deviation induced by field misplacement was carried out by calculation. Introducing exposure dose gradation, it was reduced less than 1.5nm. From measurements of a real exposed mask this technique proved to be able to stitch fields seamlessly. Major two specifications, pattern placement accuracy and critical dimension uniformity, were evaluated. Both specifications required for 150nm photomasks were fully satisfied. Availability of the photomask repeater to memory device and system on chip is discussed.
New pattern generation system, Photomask Repeater, based on i-line stepper has been developed. This system can transfer device patterns from master masks onto a photomask plate with 22mm field size. To print a chip larger than the 22mm field, stitching technology has been developed. Critical dimension error in the region where shots are stitched is the key issue of this technology. Quantification of critical dimension deviation induced by shot misplacement was carried out by calculation. Introducing exposure dose gradation, it was reduced less than 1.5nm. Form measurements of real exposed mask this technique proved to be able to stitch shots seamlessly. Major two specifications, pattern placement accuracy and critical dimension uniformity, were evaluated. Both specifications required for 150nm photomask were fully satisfied. Availability of the photomask repeater to memory device and system on chip is discussed.
We found total overlay with respect to optical lithography using an approach similar to quality control technique employed at a semiconductor factory. This approach involves an aligner performance, process quality, reticle error and overlay measurement. This paper further describes new ides for the number of machines to be used for matching and data collection period. Lastly, improvement on total overlay and a prospective view for a future aligner and its usage are also described.
We have established a new photolithographic technique called SHRINC ( Super High Resolution by I I tumi-Nation Control ) which is based on an innovative illumination system. SHRINC improves the resolution and depth-of-focus ( DOF ) by optimum arrangement of the illumination system in respect of the angle of the Ist-order of diffraction generated by the reticle pitch.
The capabilities of SHRINC have been studied by computer simulation. Results from phase shift, annular illumination, and conventional illumination are compared with those of SHRINC. The results show that using SHRINC with 0.35? m line and space patterns, the DOF, defined as the distance over which the aerial image contrast exceeds 60%, is 2. 5x larger than that obtained with conventional illumination, and almost the same as that with phase shift techniques.
In our experiments we have obtained a critical resolution of 0. 275 ? m and more than 2.8 ? m DOF with 0.35? m L/S patterns, using an i-line stepper and SHRINC illumination.
Moreover SHRINC is effective not only for simple line and space patterns, but also for complicated patterns with 0.30 or 0.35?m design rules, such as memory cell patterns or peripheral circuit patterns in the DRAM.
From these results we conclude that i-line steppers with SHRINC will make possible mass production of 64M-DRAMs with single layer resist.
Two new alignment sensors for wafer steppers are developed to attain high alignment accuracy on all layers by targeting layers that are difficult to align using the existing alignment sensor, which is based on a laser beam scanning system. The Field Image Alignment (FIA) is a bright- field TV image processing alignment system using broadband illumination. The major advantage of FIA is that due to the broadband light source used for illumination, the edges of the alignment mark can be detected without being influenced by the interference fringes formed by the photoresist. Additionally, even if the cross section of the alignment mark is asymmetrical, the asymmetry can be accurately captured and alignment at the proper position can be achieved. The Laser Interferometric Alignment (LIA) is a grating alignment system based on an optical heterodyne interferometry technique. The advantage of this sensor is that is not affected by surface irregularities such as grains because it will process only specific spatial frequency components diffracted from the alignment mark. Therefore, the spatial frequency components which are diffracted from the metallic grains will be disregarded and will not influence alignment. This allows the alignment to be successful even for low step height or deformed marks. With the development of FIA and LIA, the authors have successfully complemented the existing sensor, so that a high alignment accuracy for the mass production of VLSI with 0.5-0.35 micron rules can be achieved on most layers.