As patterns shrink to physical limits, advanced Resolution Enhancement Technologies (RET) encounter increasing challenges to ensure a manufacturable Process Window (PW). Moreover, due to the wide variety of pattern constructs for logic device layers, lithographically weak patterns (spots) become a difficult obstacle despite Source and Mask co- Optimization (SMO) and advanced OPC being applied. In order to overcome these design related lithographically weak spots, designers need lithography based simulator feedback to develop robust design rules and RET/OPC engineers must co-optimize the overall imaging capability and corresponding design lithography target. To meet these needs, a new optimization method called SmartDRO (Design Rule Optimization) has been developed. SmartDRO utilizes SMO’s Continuous Transmission Mask (CTM) methodology and optimization algorithm including design target variables in the cost function. This optimizer finds the recommended lithography based target using the SMO engine. In this paper, we introduce a new optimization flow incorporating this SmartDRO capability to optimize the target layout within the cell to improve the manufacturable process window. With this new methodology, the most advanced L/S patterns such as metal (k1 = 0.28) and the most challenging contact patterns such as via (k1 = 0.33) are enabled and meet process window requirements.
Current metal integration process normally uses hard mask for dry etch process instead of resist to compensate thin
resist thickness. As the pattern size becomes smaller, thinner resist thickness is required to get sufficient lithography
process window. But this trend increases a risk of systematic hard defect like the metal line bridge in damascene process
because of consumption in dielectric material during dry etch process.
The sub-32nm patterning with the single exposure is almost on the edge with the 193nm immersion lithography. The
smaller lithography CD makes the aerial image contrast worse, which means higher DC level in the unexposed area. This
higher DC level, latent image, can sacrifice the resist thickness in the unexposed area and this recessed resist thickness is
very harmful for the etch process with the current hard mask which may induce the metal line bridge.
Although OPC verification step checks potential hot spot during mask type out flow, there is no predictable method to
detect systematic potential defects described above. In this paper, we proposed a new method to detect such potential
defects and discussed the performance with wafer result. With this predictable model based search method, the robust
patterning process in the sub-32nm node can be developed.
Photolithography for the formerly "non-critical" implant blocking layers is becoming more challenging as edge
placement control budgets for junction definition shrink with each node. In addition to the traditional proximity
effects associated with the implant layer mask, the underlying active and gate layers can interact through a variety of
mechanisms to influence the edge placement of the developed implant layer. These mechanisms include bulk
reflectivity differences, resist thickness thin film interference effects, reflective notching from pattern sidewalls,
reflections from curved surfaces, focus differences, and more. While the use of organic developable bottom
antireflection coating (dBARC) can be effective in minimizing these influences, it does represent an added
complexity and cost, and processes are still relatively immature. Without such a dBARC, the CD variation due to
underlying layers can easily exceed 50 nm, or more than 25% of the target dimension. We propose here a
framework for modeling and correcting for these underlayer effects. The approach is based upon calibration of an
optical model representing only implant mask proximity effects and two additional optical models which represent
the effects of the underlayer topography. Such an approach can be effective in delivering much improved CD
control for complex layouts, and represents only a small impact to full-chip correction runtime.
Implant layer patterning is becoming challenging with node shrink due to decreasing critical dimension (CD) and usage
of non-uniform reflective substrates without bottom anti-reflection coating (BARC).
Conventional OPC models are calibrated on a uniform silicon substrate and the model does not consider any wafer
topography proximity effects from sub-layers. So the existing planar OPC model cannot predict the sub-layer effects
such as reflection and scattering of light from substrate and non-uniform interfaces. This is insufficient for layers without
BARC, e.g., implant layer, as technology node shrinks.
For 45-nm and larger nodes, the wafer topography proximity effects in implant layer have been ignored or compensated
using rule based OPC. When the node reached 40 nm and below, the sub-layer effects cause undesired CD variation and
resist profile change. Hence, it is necessary to model the wafer topography proximity effects accurately and compensate
them by model based OPC. Rigorous models can calculate the wafer topography proximity effects quite accurately if
well calibrated. However, the run time for model calibration and OPC compensation are long by rigorous models and
they are not suitable for full chip applications. In this paper, we demonstrate an accurate and rapid method that considers
wafer topography proximity effects using a kernel based model. We also demonstrate application of this model for full
chip OPC on implant layers.
In this paper, we report large scale three-dimensional photoresist model calibration and validation
results for critical layer models that span 32 nm, 28 nm and 22 nm technology nodes. Although
methods for calibrating physical photoresist models have been reported previously, we are unaware
of any that leverage data sets typically used for building empirical mask shape correction models. .
A method to calibrate and verify physical resist models that uses contour model calibration data sets
in conjuction with scanning electron microscope profiles and atomic force microscope profiles is
discussed. In addition, we explore ways in which three-dimensional physical resist models can be
used to complement and extend pattern hot-spot detection in a mask shape validation flow.
Metal layers have some drawbacks in building up model based OPC (MBOPC) because metal layers are mainly
composed of 2 dimensional (2D) patterns which show modeling inaccuracy and the difficulty of fragment optimization
compared with 1-dimensional patterns. As a result, metal layers have considerable hot spots such as pinch, bridge and
insufficient contact overlap. The modeling inaccuracy of 2D patterns results from a few reasons like measurement noise,
inaccurate optical simulation and empirical resist modeling etc. The fragment optimization operated by rule does not
control automatically corner rounding problems induced by small jogs of 2D patterns. The design for manufacturability
(DFM) is known to provide a solution to overcome these problems. One of engines operating the DFM is MBOPC,
which is made by an empirical process model and offers the process variation counter map simulated by the MBOPC
engine. However, the accuracy of the simulation is quite low because we cannot avoid over-corrected patterns generated
inevitably with the empirical model. In order to detect and correct the hot spots caused by the design itself, that is, the
inherent function of the DFM, it is necessary to provide the OPC engine of the physical model with the optimized
illumination condition to rule out empirical effect. Physical model is more emphasized in case of process window
simulation because of its accuracy in the edge boundary of process window. One of important function of DFM for the
metal layers is to enhance the contact overlap margin which can be influenced by the lithography process such as line
end shortening, corner rounding effect and miss-alignment. Etch process is also a significant parameter of contact
overlap. Calibrated process model is very effective to detect the insufficient contact overlap with process window.
In this paper, MBOPC of sub-45nm node metal layers is studied to provide the effective DFM engine. The DFM flow
with renewed MBOPC engine will show the improved process window and large contact overlap margin and will also
make it possible to search and correct just patterns capable of decreasing the process window by only layout defect itself.
The OPC model is very critical in the sub 45nm device because the Critical Dimension Uniformity (CDU) is so tight to
meet the device performance and the process window latitude for the production level. The OPC model is generally
composed of an optical model and a resist model. Each of them has physical terms to be calculated without any wafer
data and empirical terms to be fitted with real wafer data to make the optical modeling and the resist modeling. Empirical
terms are usually related to the OPC accuracy, but are likely to be overestimated with the wafer data and so those terms
can deteriorate OPC stability in case of being overestimated by a small cost function.
Several physical terms have been used with ideal value in the optical property and even weren't be considered because
those parameters didn't give a critical impact on the OPC accuracy, but these parameters become necessary to be applied
to the OPC modeling at the low k1 process. Currently, real optic parameter instead of ideal optical parameter like the
laser bandwidth, source map, pupil polarization including the phase and intensity difference start to be measured and
those real measured value are used for the OPC modeling. These measured values can improve the model accuracy and
stability. In the other hand these parameters can make the OPC model to overcorrect the process proximity errors without
The laser bandwidth, source map, pupil polarization, and focus centering for the optical modeling are analyzed and the
sample data weight scheme and resist model terms are investigated, too. The image blurring by actual laser bandwidth in
the exposure system is modeled and the modeling result shows that the extraction of the 2D patterns is necessary to get a
reasonable result due to the 2D patterns' measurement noise in the SEM. The source map data from the exposure
machine shows lots of horizontal and vertical intensity difference and this phenomenon must come from the
measurement noise because this huge intensity difference can't be caused by the scanner system with respect to the X-Y
intensity difference specification in the scanner. Therefore this source map should be well organized for the OPC
modeling and a manipulated source map improves the horizontal and vertical mask bias and even OPC convergence. The
focus parameter which is critical for the process window OPC and ORC should be matched to the tilted Bossung plot
which is caused by uncorrectable aberration to predict the CD change in the through focus with a new devised method.
Pupil polarization data can be applied into the OPC modeling and this parameter is also used for the unpolarized source
and the polarized source and specially this parameter helps Apodization loss to be 0 and is evaluated for the effect into
With the analysis and optimization about the model parameters the robust model is achieved in the sub 45nm device
As the minimum pitch size becomes smaller, the gate-poly critical dimension uniformity (CDU) is a critical parameter for the device performance and an important indicator of the OPC capability. From the photolithographic point of view, the root causes of increasing gate-poly CDU is due to corner rounding effects, ripples, misalignment between the gate-poly and active layers. The corner rounding effect of the gate-poly region on the active can be severe for the sub L50 device because the space between the active layer and the gate-poly layer becomes narrow.
To correct these effects caused by litho-process the advanced OPC technique and the design rule limitation should be optimized. The OPC method which can be used to improve gate-poly CDU is defined as "Litho Process-aware OPC for the Gate-Poly CDU improvement" in this paper. The pixel based simulation algorithm which gives lots of information compared to the sparse simulation algorithm is used for the OPC and ORC. The design rule for the space limitation from RX to PC is evaluated with its own litho-process model and this evaluation result has to be reflected to the design rule and the OPC recipe to manipulate the polygons is also necessary. Additionally if misalignment exists in the minimum space between the active layer and gate-poly layer during the photo process, this corner rounding effect can be more serious, so this misalignment accounted to reduce the corner rounding effect on the gate-poly CDU. The redundant field poly polygon enclosing the contact can be cut by keeping the design rule for the overlap margin between the poly layer and the contact layer. The miss-alignment effect can be considered indirectly by sizing the active layer. The OPC convergence technique is also used to reduce the ripple phenomenon close to the concave corner and line end. As a result of retargeting to accommodate a corner rounding effects, ripple effects and misalignment correction led to an improved gate-poly CDU for a sub-50nm device.