As device design rule has been made pattern size shrink, LELE (Litho-Etch- Litho-Etch) process is used in advance pattern process more and more. The CD control is one of the most critical factors for semiconductor manufacturing. However, the numbers of current in-line measurement points are not sufficient for the whole wafer CD monitoring. It’s the goal to increase inline monitor capacity without suffering process cycle time. To generate an innovation pattern to reach the goal is the purpose for the advance pattern process.<p> </p> This paper is going to introduce the detection of CD variation by using overlay metrology in LELE process. The target mark was designed from AIM (Advanced Imaging Metrology) overlay mark. By placing Layer 1 and Layer 2 AIM pattern side by side, CD variation will cause related position changed. And it is able to be detected by overlay tool. On the other hand, overlay shift will not influence this model. It has an advantage over the conventional CD measurement tool. First, the overlay tool throughput is 5~10 times faster than traditional CDSEM and the measurement time is saved. Second, we are able to measure CD and overlay at the same time. Both CD/AA performances are considered and the throughput is also gained.
Overlay metrology tool suppliers are offering today several options to their customers: Different hardware (Image Based Overlay or Diffraction Based Overlay), different target designs (with or without segmentation) or different target sizes (from 5 um to 30 um). All these variations are proposed to resolve issues like robustness of the target towards process variations, be more representative of the design or increase the density of measurements.<p> </p> In the frame of the development of a triple patterning BEOL scheme of 10 nm node layer, we compare IBO targets (standard AIM, AIMid and multilayer AIMid). The metrology tools used for the study are KLA-Tencor’s nextgeneration Archer 500 system (scatterometry- and imaging-based measurement technologies on the same tool). <p> </p>The overlay response and fingerprint of these targets will be compared using a very dense sampling (up to 51 pts per field). The benefit of indie measurements compared to the traditional scribes is discussed. The contribution of process effects to overlay values are compared to the contribution of the performance of the target. Different targets are combined in one measurement set to benefit from their different strengths (performance vs size). <p> </p>The results are summarized and possible strategies for a triple patterning schemes are proposed.
Advanced design nodes require more complex lithography techniques, such as double patterning, as well as advanced
materials like hard masks. This poses new challenge for overlay metrology and process control. In this publication
several step are taken to face these challenges. Accurate overlay metrology solutions are demonstrated for advanced
Most fabrication facilities today use imaging overlay measurement methods, as it has been the industry’s reliable workhorse for decades. In the last few years, third-generation Scatterometry Overlay (SCOL™) or Diffraction Based Overlay (DBO-1) technology was developed, along another DBO technology (DBO-2). This development led to the question of where the DBO technology should be implemented for overlay measurements. Scatterometry has been adopted for high volume production in only few cases, always with imaging as a backup, but scatterometry overlay is considered by many as the technology of the future. In this paper we compare imaging overlay and DBO technologies by means of measurements and simulations. We outline issues and sensitivities for both technologies, providing guidelines for the best implementation of each. For several of the presented cases, data from two different DBO technologies are compared as well, the first with Pupil data access (DBO-1) and the other without pupil data access (DBO-2). Key indicators of overlay measurement quality include: layer coverage, accuracy, TMU, process robustness and robustness to process changes. Measurement data from real cases across the industry are compared and the conclusions are also backed by simulations. Accuracy is benchmarked with reference OVL, and self-consistency, showing good results for Imaging and DBO-1 technology. Process sensitivity and metrology robustness are mostly simulated with MTD (Metrology Target Designer) comparing the same process variations for both technologies. The experimental data presented in this study was done on ten advanced node layers and three production node layers, for all phases of the IC fabrication process (FEOL, MEOL and BEOL). The metrology tool used for most of the study is KLA-Tencor’s Archer 500LCM system (scatterometry-based and imaging-based measurement technologies on the same tool) another type of tool is used for DBO-2 measurements. <p> </p>Finally, we conclude that both imaging overlay technology and DBO-1 technology are fully successful and have a valid roadmap for the next few design nodes, with some use cases better suited for one or the other measurement technologies. Having both imaging and DBO technology options available in parallel, allows Overlay Engineers a mix and match overlay measurement strategy, providing back up when encountering difficulties with one of the technologies and benefiting from the best of both technologies for every use case.
The performance of overlay metrology as total measurement uncertainty, design rule compatibility, device correlation, and measurement accuracy has been challenged at the 2× nm node and below. The process impact on overlay metrology is becoming critical, and techniques to improve measurement accuracy become increasingly important. We present a methodology for improving the overlay accuracy. A propriety quality metric, Qmerit, is used to identify overlay metrology measurement settings with the least process impacts and reliable accuracies. Using the quality metric, a calibration method, Archer self-calibration, is then used to remove the inaccuracies. Accuracy validation can be achieved by correlation to reference overlay data from another independent metrology source such as critical dimension–scanning electron microscopy data collected on a device correlated metrology hybrid target or by electrical testing. Additionally, reference metrology can also be used to verify which measurement conditions are the most accurate. We provide an example of such a case.
One of the main issues with accuracy is the bias between the overlay (OVL) target and actual device OVL. In this study, we introduce the concept of device-correlated metrology (DCM), which is a systematic approach to quantify and overcome the bias between target-based OVL results and device OVL values. In order to systematically quantify the bias components between target and device, we introduce a new hybrid target integrating an optical OVL target with a device mimicking critical dimension scanning electron microscope (CD-SEM) target. The hybrid OVL target is designed to accurately represent the process influence on the actual device. In the general case, the CD-SEM can measure the bias between the target and device on the same layer after etch inspection (AEI) for all layers, the OVL between layers at AEI for most cases and after develop inspection for limited cases such as double-patterning layers. The results have shown that for the innovative process compatible hybrid targets the bias between the target and device is small, within the order of CD-SEM noise. Direct OVL measurements by CD-SEM show excellent correlation between CD-SEM and optical OVL measurements at certain conditions. This correlation helps verify the accuracy of the optical measurement results and is applicable for the imaging base OVL method using several target types advance imaging metrology, advance imaging metrology in die OVL, and the scatterometrybase OVL method. Future plans include broadening the hybrid target design to better mimic each layer process conditions such as pattern density. Additionally, for memory devices we are developing hybrid targets which enable other methods of accuracy verification.
As overlay margins shrink for advanced process nodes, a key overlay metrology challenge is finding the measurement conditions which optimize the yield for every device and layer. Ideally, this setup should be found in-line during the lithography measurements step. Moreover, the overlay measurement must have excellent correlation to the device electrical behavior. This requirement makes the measurement conditions selection even more challenging since it requires information about the response of both the metrology target and device to different process variations. In this work a comprehensive solution for overlay metrology accuracy, used by UMC, is described. This solution ranks the different measurement setups by their accuracy, using Qmerit, as reported by the Archer 500. This ranking was verified to match device overlay using electrical tests. Moreover, the use of Archer Self Calibration (ASC) allows further improvement of overlay measurement accuracy.
Overlay metrology performance as Total Measurement Uncertainty (TMU), design rule compatibility, device correlation and measurement accuracy are been challenged at 2x nm node and below. Process impact on overlay metrology becoming critical, and techniques to improve measurement accuracy becomes increasingly important. In this paper, we present an innovative methodology for improving overlay accuracy. A propriety quality metric, Qmerit, is used to identify overlay metrology measurement settings with least process impacts and reliable accuracies. Using the quality metric, an innovative calibration method, ASC (Archer Self Calibration) is then used to remove the inaccuracies. Accuracy validation can be achieved by correlation to reference overlay data from another independent metrology source such as CDSEM data collected on DCM (Device Correlated Metrology) hybrid target or electrical testing. Additionally, reference metrology can also be used to verify which measurement conditions are the most accurate. In this paper we bring an example of such use case.
One of the main issues with overlay error metrology accuracy is the bias between results based on overlay (<strong>OVL</strong>) targets and actual device overlay error. In this study, we introduce the concept of <strong>Device Correlated Metrology</strong> (<strong>DCM</strong>), which is a systematic approach to quantifying and overcoming the bias between target-based overlay results and device overlay issues. For systematically quantifying the bias components between target and device, we introduce a new hybrid target integrating an optical <strong>OVL</strong> target with a device mimicking <strong>CD-SEM</strong> (Critical Dimension – Scanning Electron Microscope) target. The hybrid <strong>OVL</strong> target is designed to accurately represent the process influence found on the real device. In the general case, the <strong>CD-SEM</strong> can measure the bias between target and device on the same layer at AEI (After Etch Inspection) for all layers, the OVL between layers at AEI for most cases and at ADI (After Develop Inspection) for limited cases such as DPL (Double Patterning Lithography). The results shown demonstrate that for the new process compatible hybrid targets the bias between target and device is small, of the order of <strong>CD-SEM</strong> measurement uncertainty. Direct <strong>OVL</strong> measurements by <strong>CD-SEM</strong> show excellent correlation with optical <strong>OVL</strong> measurements in certain conditions. This correlation helps verify the accuracy of the optical measurement results and is applicable for imaging based <strong>OVL</strong> metrology methods using <strong>AIM</strong> or <strong>AIMid OVL</strong> targets, and scatterometry-based overlay methods such as SCOL (Scatterometry <strong>OVL</strong>). Future plans include broadening the hybrid target design to better mimic each layer’s process conditions such as pattern density. We are also designing hybrid targets for memory devices.
In order to fulfill the ever tightening requirements of advanced node overlay budgets, overlay metrology is becoming more and more sensitive to even the smallest imperfections in the metrology target. Under certain circumstances, inaccuracy due to such target imperfections can become the dominant contribution to the metrology uncertainty and cannot be quantified by the standard TMU contributors. In this paper we describe a calibration method that makes the overlay measurement robust to target imperfections without diminishing its sensitivity to the target overlay. The basic assumption of the method is that overlay measurement result can be approximated as the sum of two terms: the accurate overlay and the measurement inaccuracy (independently of the conventional contributors). While the first term (the “real overlay”) is robust it is known that the overlay target inaccuracy depends on the measurement conditions. This dependence on measurement conditions is used to estimate quantitative inaccuracy by means of the overlay quality merit which was described in previous publications. This paper includes the theoretical basis of the method as well as experimental validation.
The semiconductor industry is moving toward 20nm nodes and below. As the Overlay (OVL) budget is getting tighter at these advanced nodes, the importance in the accuracy in each nanometer of OVL error is critical. When process owners select OVL targets and methods for their process, they must do it wisely; otherwise the reported OVL could be inaccurate, resulting in yield loss. The same problem can occur when the target sampling map is chosen incorrectly, consisting of asymmetric targets that will cause biased correctable terms and a corrupted wafer. Total measurement uncertainty (TMU) is the main parameter that process owners use when choosing an OVL target per layer. Going towards the 20nm nodes and below, TMU will not be enough for accurate OVL control. KLA-Tencor has introduced a quality score named ‘Qmerit’ for its imaging based OVL (IBO) targets, which is obtained on the-fly for each OVL measurement point in X & Y. This Qmerit score will enable the process owners to select compatible targets which provide accurate OVL values for their process and thereby improve their yield. Together with K-T Analyzer’s ability to detect the symmetric targets across the wafer and within the field, the Archer tools will continue to provide an independent, reliable measurement of OVL error into the next advanced nodes, enabling fabs to manufacture devices that meet their tight OVL error budgets.
One of the main challenges related to the growing number of Litho layers and most specifically to Multi Patterning, is the ability to align to many layers at once. In the past things were simple, the alignment tree was set so that every layer aligns to one layer and at the most is measured versus two layers, such as contact to poly and Isolation. Today, even at the 20 nm node there are double and triple patterning for critical layers such as Isolation, poly, contact and Metal 1. This forces a much more complex alignment tree and Overlay (OVL) measurement. Layers are sometimes aligned to an average of previous layers, to different layers at different orientations and disposition is done based on several measurements. This growing challenge increases the number of Overlay measurements significantly, increases the target area and present the need to make many measurement from different layers consistent. Another challenge is the increased number of recipes and the need for flexible alignment tree scheme during development. These challenges are addressed by Multi layer targets such as Triple AIM, Multilayer AIMid and the Blossom and micro-Blossom targets where alignment marks from multiple patterning steps and layers were densely populated. A single OVL reading is calculated by the metrology tool on a selected pair or multiple pair average<sup>1</sup>. Here we propose the Multi-Layer measurement that provides an additional degree of metrology and solution to these challenges: in one measurement several overlay results are achieved, the results are always self-consistent. It allows at the same measurement grab to look back and disposition previous layers after their processing was completed. It allows a flexible alignment tree without the need to add or change targets, even during ramp and production. It reduces the number of recipes that need to be created and managed. And it also reduces significantly the area needed for the targets. In this paper we will show recent results from IMEC, on Back-End (BE) stack of four layers including one double patterning layer. We compared several target sizes, showing that such a target can fit within the Indie requirements of 10x10 μm. Results show that there is not a lot of need to compromise on performance in order to get good Multi-Layer measurements. Eventually we will describe process compatible targets which are needed more in the Front End (FE) layers. Looking forward at the increased complexity needed for future nodes and multiple pitch splitting lithography, it is encouraging to see that for Overlay we can simplify metrology instead of making it follow the complexity trend.
This course explains basic principles of metrology of image placement for applications to registration, alignment, and overlay in IC manufacture. Starting with IC Design Rules, and device pattern size and placement as their basis, this course outlines a systematic approach to dimensional metrology. Device pattern variation in mask-making, lithography imaging, image recoding, and image transfer, and down-stream wafer processing, are discussed leading to requirements of dimension metrology and control. Expectations in metrology of image placement are examined in the context of semiconductor design and manufacturing paradigm: device invariance in transformations of symmetry and translation, universal coordinate system, and absolute scale being the foundation of IC design. The same attributes built into IC design are maintained in production by the use of isoplanatic lithography systems, dimensionally stable masks, stages, and wafers, control of long distance scale and, of course, spatially uniform semiconductor processing. The key performance metrics for metrology of image placement are defined and illustrated in applications to improving robustness and accuracy in production environment. Systematic quantitative validation of those expectations for metrology systems and targets being measured, with complementary validation means and measurement technology, lay the foundation for certifiably accurate metrology of image placement and comprehensive control of overlay in IC manufacture.