We report a systematic study of the feasibility of using directed self-assembly (DSA) in real product design for 7-nm fin field effect transistor (FinFET) technology. We illustrate a design technology co-optimization (DTCO) methodology and two test cases applying both line/space type and via/cut type DSA processes. We cover the parts of DSA process flow and critical design constructs as well as a full chip capable computational lithography framework for DSA. By co-optimizing all process flow and product design constructs in a holistic way using a computational DTCO flow, we point out the feasibility of manufacturing using DSA in an advanced FinFET technology node and highlight the issues in the whole DSA ecosystem before we insert DSA into manufacturing.
Performing model-based optical proximity correction (MBOPC) on layouts has become an integral part of
patterning advanced integrated circuits. Earlier technologies used sparse OPC, the run times of which explode when the
density of layouts increases. With the move to 45 nm technology node, this increase in run time has resulted in a shift to
dense simulation OPC, which is pixel-based. The dense approach becomes more efficient at 45nm technology node and
beyond. New OPC model forms can be used with the dense simulation OPC engine, providing the greater accuracy
required by smaller technology nodes. Parameters in the optical model have to be optimized to achieve the required
accuracy. Dense OPC uses a resist model with a different set of parameters than sparse OPC. The default search ranges
used in the optimization of these resist parameters do not always result in the best accuracy. However, it is possible to
improve the accuracy of the resist models by understanding the restrictions placed on the search ranges of the physical
parameters during optimization. This paper will present results showing the correlation between accuracy of the models
and some of these optical and resist parameters. The results will show that better optimization can improve the model
fitness of features in both the calibration and verification set.
As critical dimensions (CDs) approach (lambda) /two, the use of optical proximity correction (OPC)
relies heavily on the ability of the mask vendor to resolve the OPC structures consistently. When an OPC
model is generated the reticle and wafer-processing errors are merged, quantified, and fit to a theoretical
model. The effectiveness of the OPC model depends greatly on model fit and therefore consistency in the
reticle and wafer processing. Variations in either process can 'break' the model resulting in the wrong
corrections being applied. Reticle manufacturing variables that effect OPC models are exposure tool
resolution, etch process effects, and process push (pre-bias of the fractured data). Most of the errors from
these reticle-manufacturing variables are seen during model generation, but there are some regions that are
not, and fail to be accounted for such as extremes in the line ends. Since these extreme regions of the mask
containing the OPC have a higher mask error enhancement factor (MEEF) than that of the rest of the mask,
controlling mask-induced variables is even more important. The phase shift mask (PSM) is one of the most
effective approaches to improve ArF lithography performance. MoSi or SiON dry etching technology play
an important role to fabricate phase shift masks, such as space bias type Alternating (Alt.) PSM and
chrome-less phase shift masks (CPL). The profile of the etched quartz affects the lithography performance.
In this paper we evaluate the nominal influences of the MoSi or SiON profiles on pattering and OPC by
rigorous electromagnetic field simulations. The influence of the MoSi or SiON profile is investigated by
evaluating imaginary masks. In this experiment, we simulated attenuated PSMs with tapered sidewalls,
high round and micro-trenches of varying depths. OPC modeling performances of the imaginary masks are
measured by the OPC print image CD and model fitting results. I compare the result of print image CD
with simulation. I investigate how well the OPC print image CD measurement corresponds to the
simulation. Mask CD error and sidewall angle strongly affect the OPC modeling performance. However,
micro-trench does not affect the OPC performance. This paper quantifies the effects reticle processing has
on the OPC model generation, and also mask CD variations and variable sidewall angles affect the OPC
print image CD and OPC model fitting for attenuated PSMs, micro trench depth does not play an important
role for OPC print image CD and OPC model fitting.
As lithography pushes to smaller and smaller features under the guidance of Moore's Law, patterned features smaller than the wavelength of light must be routinely manufactured. Lithographic yield in this domain is directly improved with the application of OPC (Optical and Process Correction) to the pattern data. Such corrections generally assume that the mask can reproduce these features exactly. The Mask Error Enhancement Factor (MEEF) serves to amplify mask errors, and can reduce the benefits of OPC in some circumstances. In this paper, we present the characterization of the MEEF for 65nm technology attenuated phase shift mask to figure out how to better set mask specs from an OPC perspective and how to measure the masks relative to these specs and try to figure out new ways to reduce model sensitivity to mask deviations for metal level.
As the potentials of experimental studies are still limited, a predictive resist image simulation of Immersion lithography is very important for a better understanding of the technology. One of the most critical issues in Immersion lithography is the description of the influence of immersion which is the presence of a uniform liquid layer between the last objective lens and the photo resist, on optical lithography. It enables the real part of the index of refraction in the image space, and the numerical aperture of the projection lens, to be greater than unity. Therefore, it is virtually involves Maxwell vector solution approach, including polarization effects and arbitrary thin film multi-layers. This paper discusses the improvement in process window afforded by immersion under a variety of conditions, including 193nm and 157nm, Off-axis illumination, Attenuated Phase Shift Mask for 65nm and 45nm technology node. Comparisons with dry and liquid lithography simulations are used to evaluate the availability and the performance of the proposed approach. The implemented resist simulation approach is examined the impact to the process window of variations in liquid refractive index as well.
Critical features of a product layout like isolated structures and complicated two-dimensional situations including line ends have often a smaller process window compared to regular highly nested features. It has been observed that the application of optical proximity corrections (OPC) can create yet more aggressive layout situations. Although corrected layouts meet the target contour under optimal exposure conditions, the process window of these structures under non-optimal conditions is thereby potentially reduced. This increases the risk of shorts and opens in the resist images of the designs under non-optimal exposure conditions. The requirement from a lithographer's point of view is to conduct a correction that considers the process window aspect besides the desired target contour. The present study investigates a concept of using the over-dose and under-dose responses of the simulated image of an exposed structure to optimize the correction value. The simulations describing the lithographic imaging process are based on an enhanced variable threshold model (VTRE). The placement error of the simulated edge of a structure is usually corrected for the nominal dose and focus settings. In the new concept the effective edge placement error is defined as the average of the edge placement errors for the over-dose and the edge placement error for the under-dose conditions. If a specific layout has a very non-symmetric response to over-/under exposure for the evaluated condition, it is prone to a certain failure mechanism (open or short). Hence calculating the average of the edge placement errors will shift the effective correction towards a layout with larger process window. The paper evaluates this concept for 100 nm ground rules and 193 nm lithography conditions. Examples of corrected layouts are presented together with experimental data. The limitations of the approach are discussed.
The attenuated phase shift mask has been sued to delineate 0.22 micrometers contact hole structures for 0.18micrometers technology. Using a scanner with a high NA of 0.68, this is equivalent to a k<SUB>1</SUB> value of 0.60. As device shrinks down to 0.13 micrometers technology, 0.16 micrometers contact holes are to be printed with sufficient process latitudes. Using the existing high NA scanner, the k<SUB>1</SUB> value is a low 0.44. Simulations were done using PROLITH/3D software, and the results show better performance for isolated holes. Higher mask transmissions are required to improve the aerial image of the dense holes. Experimentation was conducted to print 0.16micrometers contact holes using moderate and low (sigma) settings. 6 percent APSM was used with 0.16micrometers , 0.18micrometers and 0.20micrometers contact hole patterns biased by 0.04micrometers , 0.06micrometers and 0.08micrometers . Impact of these parameters on mask error enhancement factor were discussed.