With the push toward the 32nm node, OPC modeling must respond in kind with additional accuracy enhancements.
One area of lithographic modeling that has basically gone unchecked is mask fidelity. Mask linearity is typically built
into the OPC model since the calibration data contain this information, but mask pattern fidelity is almost impossible to
quantify for OPC modeling. Mask fidelity is the rounding and smoothing of the mask features relative to the post-OPC
layout intent, and there is no robust metric available to quantify these effects. With the introduction of contour-based
model calibration, mask fidelity modeling is possible. This work evaluates techniques to quantify mask modeling and
methods to gauge the accuracy improvement that mask fidelity modeling would project into the lithographic process
using contour-based mask model calibration.
As design rules shrink, there is an unavoidable increase in the complexity of OPC/RET schemes required to enable
design printability. These complex OPC/RET schemes have been facilitating unprecedented yield at k<sub>1</sub> factors
previously deemed "unmanufacturable", but they increase the mask complexity and production cost, and can introduce
yield-detracting errors. The most common errors are found in OPC design itself, and in the resulting patterning
robustness across the process window. Two factors in the OPC design process that contribute to these errors are a) that
2D structures used in the design are not sufficiently well-represented in the OPC model calibration test pattern suite, and
b) that the OPC model calibration is done only at the nominal process settings and not across the entire focus-exposure
This work compares two alternative methods for calibrating OPC models. The first method uses a traditional industry
flow for making CD measurements on standard calibration target structures. The second method uses 2D contour
profiles extracted automatically by the CD-SEM over varying focus and exposure conditions. OPC models were
developed for aggressive quadrupole illumination conditions (k<sub>1</sub>=0.35) used in 65nm- and 45nm-node logic gate
patterning. Model accuracy improvement using 2D contours for calibration through the process window is
demonstrated. Additionally this work addresses the issues of automating the contour extraction and calibration process,
reducing the data collection burden with improved calibration cycle time.
This paper describes a method to automatically distinguish between line and space for 1:1 line space patterns in mask
metrology. As the number of measurements typically performed on a reticle is significantly higher than on a wafer,
automated CAD based CD-SEM recipe creation is essential. Such recipes typically use synthetic pattern recognition
targets instead of SEM based pattern recognition targets. Therefore, a possible different contrast between lines and
spaces on a mask cannot be utilized for distinguishing lines from spaces. We demonstrate an algorithm solution based
on the analysis of the SEM waveform profiles to identify potential L/S mix-ups and correct them automatically. The
solution allows fully automated CAD based offline recipe creation with a high success rate of distinction between lines
and spaces for 1:1 pitch cases without the necessity of editing recipes on the tool in advance of performing the
With the advent of system-on-chip (SOC) devices, resolving typical problems of composite designs is getting more urgent. The continuous effort for achieving tighter critical dimension (CD) tolerances together with the known phenomena of pattern density loading makes the mask fidelity issue for SOC technology a unique and prominent issue. The typical characteristic of an SOC with respect to CD control is the diversity of linewidths and pattern density over the chip. This paper presents the metrology software called Linewidth Bias Monitor (LBM) as a method to characterize pattern-loading effects on an SOC.
Using a failure analysis-driven yield enhancements concept, based on an optimization of the mask manufacturing process and UV reticle inspection is studied and shown to improve the contact layer quality. This is achieved by relating various manufacturing processes to very fine tuned contact defect detection. In this way, selecting an optimized manufacturing process with fine-tuned inspection setup is achieved in a controlled manner. This paper presents a study, performed on a specially designed test reticle, which simulates production contact layers of design rule 250nm, 180nm and 150nm. This paper focuses on the use of advanced UV reticle inspection techniques as part of the process optimization cycle. Current inspection equipment uses traditional and insufficient methods of small contact-hole inspection and review.