With the increase of litho-etch steps the industry requires metrology to deliver solutions to improve throughput of overlay measurements without impacting accuracy. ASML’s YieldStar 350E is capable of utilizing targets, which can measure the overlay of multiple layers simultaneously. For the work discussed in this paper, an evaluation is performed on Logic product wafers using both single-layer and multi-layer (MLT) quad type targets (able to capture up to four litho-etch steps). Different target types were compared in terms of Move-and-Acquire (MA) time, residual and matching to SEM. Using the MLT targets, an MA time improvement of 56% was demonstrated on the singlelayer. The maximum delta between the overlay residual among the YieldStar targets after applying an high order model was shown to be 0.05 nm. In comparison to after-etch overlay, the correlation of the MLT target was determined with an R<sup>2</sup> >; 0.95 using a set-get wafer with induced 10 nm overlay range. On a normal production wafer, the correlation was R<sup>2</sup> > 0.67, which is high on a wafer without induced overlay. The comparison of modeling parameters between SEM and MLT targets shows a good match (< 0.16nm) as well.
Immersion lithography is being extended beyond the 10-nm node and the lithography performance requirement needs to be tightened further to ensure good yield. Amongst others, good on-product focus control with accurate and dense metrology measurements is essential to enable this. In this paper, we will present new solutions that enable onproduct focus monitoring and control (mean and uniformity) suitable for high volume manufacturing environment. We will introduce the concept of pure focus and its role in focus control through the imaging optimizer scanner correction interface. The results will show that the focus uniformity can be improved by up to 25%.
As a result of the continuously shrinking features of the integrated circuit, the overlay budget requirements have become very demanding. Historically, overlay has been performed using metrology targets for process control, and most overlay enhancements were achieved by hardware improvements. However, this is no longer sufficient, and we need to consider additional solutions for overlay improvements in process variation using computational methods. In this paper, we present the limitations of third-order intrafield distortion corrections based on standard overlay metrology and propose an improved method which includes a prediction of the device overlay and corrects the lens aberration fingerprint based on this prediction. For a DRAM use case, we present a computational approach that calculates the overlay of the device pattern using lens aberrations as an additional input, next to the target-based overlay measurement result. Supporting experimental data are presented that demonstrate a significant reduction of the intrafield overlay fingerprint.
In this paper we present the limitations of 3rd order distortion corrections based on standard overlay metrology and propose a new method to quantify and correct the cold-lens aberration fingerprint. As a result of continuous shrinking features of the integrated circuit, the overlay budget requirements have become very demanding. Historically, most overlay enhancements were achieved by hardware improvements. However there also is a benefit in the computational approach, and so we looked for solutions for overlay improvements in process variation with computational applications.