One of the promising areas in the field of image processing and analysis is the hardware implementation of neural network for processing and analyzing of images based on FPGA technologies. The structural scheme of the multifunctional calculator was developed. It contains MxN cells in the form of matrix, a formation block of signs that has N control nodes, input of clock impulses, input of reset, output of common feature of zero and outputs of features of zero by columns and rows of matrix. The described structure is a classifier and it was written to the FPGA crystal1.
The main task is to provide processing and analysis of images in real time. Hardware implementation allows to use it in many types of activities: biomedical engineering, industry, aerospace sphere, etc2.