We have previously presented the smallest and fastest 6 Transistor (6T)-Static Random Access Memories (SRAM) bitcells for System-on-Chip (SoC) high-density (HD) memories in 0.18 μm and 0.13 μm technologies. Our 1.87 μm<sup>2</sup> 6TSRAM bitcell with cell current of 47 μA and industry lowest soft error rate (0.35 FIT/Kbit) is used to assemble memory blocks embedded into SoC designs in 0.13 μm process technology. Excellent performance is achieved at a low overall cost, as our bitcells are based on standard CMOS process and demonstrate high yields in manufacturing. This paper discusses our methodology of embedded SRAM bitcell design. The key aspects of our approach are:
1) judicious selection of tightest achievable yet manufacturable design rules to build the cell; 2) compatibility with standard Optical Proximity Correction (OPC) flow; 3) use of parametric testing and yield analysis to achieve excellent design robustness and manufacturability. A thorough understanding of process limitations, particularly those related to photolithography was critical to the
successful design and manufacturing of our aggressive, yet robust SRAM bitcells. The patterning of critical layers, such as diffusion, poly gate, contact and metal 1 has profound implications on functionality, electrical performance and manufacturability of memories.
We have conducted the development of SRAM bitcells using two approaches for OPC: a) "manual’ OPC, wherein the bitcell layout of each of the critical layers is achieved using iterative improvement of layout & aerial image simulation and b) automated OPC-compatible design, wherein the drawn bitcell layout becomes a subject of a full chip OPC. While manual-OPC remains a popular option, automated OPC-compatible bitcell design is very attractive, as it does not require additional development costs to achieve fab-to-fab portability. In both cases we have obtained good results with respect to patterning of the critical layers, electrical performance of the bitcell and memory yields. A critical part of our memory technology development effort is the design of memory-specific test structures that are
used for: a) verifying electrical characteristics of SRAM transistors and b) confirming the robustness of the design rules used within the SRAM cell. In addition to electrical test structures, we have a fully functional SRAM test chip called RAMPCM that is composed of sub-blocks each designated to evaluate the robustness of a specific critical design rule used within the bitcells. The results from the electrical testing and RAMPCM yield analysis are used to identify
opportunities for improvements in the layout design.
The paper will also suggest some techniques that can result in more design friendly OPC solutions. Our work indicates that future IC designs can benefit from an automated OPC tool that can intelligently handle layout modifications according to design priorities.
We have been exploring alternating aperture phase-shifting masks for Application Specific Integrated Circuit poly gate CD's below 100 nm. The implementation is dark field altPSM with a complementary bright field binary 'trim' mask. The alternating phase shift approach is attractive because of the potential for improved resolution, increased individual process windows, and reduced developed resist line edge roughening (LER) needed for superior device performance. This can be accomplished with moderately low exposure tool numerical aperture (NA). However, these improvements must justify the increased mask cost, throughput reduction of dual mask, and the necessity of optical and process pattern correction (OPC) of 2 masks. Compared to the single reticle non-strong phase shift approach, the altPSM option potentially has new modes of failure: image intensity imbalance between the 0 and 180 degree phases, phase error sensitivity, and quartz sidewall angle sensitivity, all as a function of feature p9itch. Additionally, the high coherence required to print altPSM sensitivities plus corrections for mask writing inaccuracies, lithography printing inaccuracies, and etch inhomogeneities. Manufacturing with altPSM adds additional CD uniformity requirements across the chip. In this paper we discuss the performance of a 193 nm altPSM dual mask set's printing across the exposure slit of an ASML/950 scanner in the 80 nm regime. We will show how wafer level image placement error varies with focus and pitch across the scanner slit. We will discuss 3 methods of OPC correction as a function of CD and pitch across the scanner slit, their self-agreement, and OPC grid requirements. We will also present OPC corrected common process windows across the slit.