Adders are the core element in arithmetic circuits like subtracters, multipliers, and dividers. Optimization of adders can be
achieved at device, circuit, architectural, and algorithmic levels. In this paper we present a new optimize full adder circuit
structure that provides an improved performance compared to standard and mirror types adder structures. The performance
of this adder in terms of power, delay, energy, and yield are investigated. This paper also proposes a novel simulation setup
for full adder cells that is suitable for analyzing full adder cells at the high frequency. The simulation results of this structure
will take into account the process variations for a 90 nm CMOS process and present results based on post-layout simulation
using Cadence and Synopsys tools.