Chrome-less Phase Lithography (CPL) was introduced as a potential strong Resolution Enhancement Technology (RET) for 90nm to 65nm node critical layers. One of the important issue with trench type chrome-less mask manufacturing for post structure is quartz defect detection capability. This study will focus on half pitch 80nm (1X) design node and apply different trench sizes and programmed defect sizes. All test patterns will be inspected on KLA-Tencor TeraScan576 inspection tool with both standard Die-to-Die (DD) and TeraPhase DD inspection modes to determine defect detection capability. All programmed defects will also be simulated on the Zeiss AIMS Fab-193 to determine wafer CD error. Finally, we will establish the relationship between trench size, defect detection capability and printability, and summarize the chrome-less mask quartz defect detection capability for 80nm post structure application.
CPL technology is one of the powerful methods for Resolution Enhancement Technology. With high NA and strong off-axis illumination CPL has a very high resolution and is capable of printing complex 2D patterns. Image using off-axis illumination with an attenuated phase shift mask can also improve process latitude. We can combine two technologies in one mask with same off-axis illumination condition to have more flexible application. Normally CPL technology is applied in binary mask and Qz is etched for 180 degree phase. To fulfill this hybrid mask we can apply Qz etch in current normal attenuate PSM blank and E-Beam 2nd writing is also can be applied for the zebra structure. To form the different application in different area we use 5 times writing in this hybrid mask process. Also the Qz etching process is very important because the Qz etching is strongly related to the Cr-Mosi-Qz three layer profile. So a L9 DOE has been applied for Qz etching parameter fine tuning. We will optimize the phase uniformity, phase linearity, profile, CD linearity and CD proximity through the DOE.
Chemically amplified resists, CAR, and 50kV e-beam writers have been applied for the most advance mask manufacturing. To fulfill the requirement of 65nm generation a good performance resist played an important role. In this work, two advanced positive and negative CAR resist has been evaluated for 65nm photomask process with a 50kV e-beam pattern generator in an advanced process line. For 65nm node not only the resolution is needed to be improved but also the cirtical dimension(CD) control will be more critical than previous generation. So the evaluation is focus on the CD performance, resolution, profile, e-beam sensitivity, line edge roughness(LER), etc.
In this paper we describe, from the user's point of view, how Inverse Lithography Technology (ILT) differs from Optical Proximity Correction (OPC). We show simulation and experimental results from 90nm and 65nm semiconductor nodes, comparing ILT-generated masks and OPC-generated masks for real-life layouts, in a production environment. In addition, we discuss issues related to complexity and manufacturability of ILT-generated masks.
To extend the application of ArF exposure tool, CPL is one of the most powerful technologies for the resolution enhancement. From previous study, the 2nd level writing by E-Beam writer has been developed to ensure the manufacturability of CPL process. To fulfill the application of CPL Mask, we implemented this technology for 65nm DRAM patterning. First we studied the performance and characteristics of CPL mask with optimized exposure illumination setting for the desired pattern and dimension of 65nm DRAM. Then the mask data for CPL mask manufacture has been generated by modeled pattern decomposition approach together with rule and modeled OPC. This was accomplished by using an engine named MaskWeaver. For the manufacture of CPL mask, we used a binary mask and the Qz was etched for the 180 degrees phase difference. We utilized a 2nd level writing by an E-Beam writer to make the zebra pattern that was generated by the engine for the optimized patterning performance. The exposure tool we utilized for the verification of wafer patterning is an advanced 193nm exposure system. The process performance indexes such as MEEF, process window, CD uniformity were collected to show the capability of CPL process. Also, simulation and empirical data were compared to verify the performance of CPL technology. So by using an optimized CPL technology included mask data generation skill, mask making specifications, and ArF illumination optimization, we can meet the manufacture requirement of 65nm DRAM.
The chromeless phase lithography (CPL) is a potential technology for low k1 optical image. For the CPL technology, we can control the local transmission rate to get optimized through pitch imaging performance. The CPL use zebra pattern to manipulate the pattern local transmission as a tri-tone structure in mask manufacturing. It needs the 2nd level writing to create the zebra pattern. The zebra pattern must be small enough not to be printed out and the 2nd writing overlay accuracy must keep within 40nm. The request is a challenge to E-beam 2nd writing function. The focus of this paper is in how to improve the overlay accuracy and get a precise pattern to form accurate pattern transmission. To fulfill this work several items have been done. To check the possibility of contamination in E-Beam chamber by the conductive layer coating we monitor the particle count in the E-Beam chamber before and after the coated blank load-unload. The conductivity of our conductive layer has been checked to eliminate the charging effect by optimizing film thickness. The dimension of alignment mark has also been optimized through experimentation. And finally we checked the PR remain to ensure sufficient process window in our etching process. To verify the performance of our process we check the 3D SEM picture. Also we use AIMs to prove the resolution improvement capability in CPL compared to the traditional methods-Binary mask and Half Tone mask. The achieved overlay accuracy and process can provide promising approach for NGL reticle manufacturing of CPL technology.