This paper describes the simulation results of a high performance readout integrated circuit (ROIC) designed for long wave infrared (LWIR) detectors, which has high dynamic range (HDR). A special architecture is used to the input unit cell to accommodate the wide scene dynamic range requirement, thus providing over a factor of 70dB dynamic range. A capacitive feedback transimpedance amplifier (CTIA) provides a low noise detector interface circuit capable of operating at low input currents and a folded cascade amplifier with a gain of 73dB is designed. A 6.4pF integration capacitor is used for supporting a wide scene dynamic range, which can store 80Me. Because of the restriction of the layout area, four unit cells will share an integration capacitor. A sample and hold capacitor is also part of the input unit cell architecture, which allows the infrared focal plane arrays (IRFPA) to be operated in full frame snapshot mode and provides the maximum integration time available. The integration time is electronically controlled by an external clock pulse. The simulation results show that the circuit works well under 5V power supply and the nonlinearity is calculated less than 0.1%. The total power dissipation is less than 150mW.
HgCdTe electron injection avalanche photodiodes (e-APDs) work at linear mode. A weak optical current signal is amplified orders of magnitude due to the internal avalanche mechanism and it has been demonstrated to be one of the most promising methods to focal-plane arrays (FPAs) for low-flux like hyper-spectral imaging and high-speed applications such as active imaging. This paper presents the design of a column-shared ADC for cooled e-APDs FPA. Designing a digital FPA requires fulfilling very stringent requirements in terms of power consumption, silicon area and speed. Among the various ADC architectures sigma-delta conversion is a promising solution for high-performance and medium size FPA such as 128×128. The performance of Sigma-delta ADC rather relies on the modulator structure which set over-sampling and noise shaping characteristics than on critical analog circuits. This makes them quite robust and flexible. A multistage noise shaping (MASH) 2-1 single bit architecture sigma-delta conversion with switched-capacitor circuits is designed for column-shared ADC, which is implanted in the GLOBALFOUNDRIES 0.35um CMOS process with 4-poly and 4-metal on the basis of a 100um pixel pitch. It operates under 3.3V supply and the output range of the quantizer is 2V. A quantization noise subtraction circuit in modulator is designed to subtract the quantization noise of first-stage modulator. The quantization noise of the modulator is shaped by a high-pass filter. The silicon area and power consumption are mainly determined by the decimation low pass filter. A cascaded integrator-comb (CIC) filter is designed as the digital decimator filter. CIC filter requires no multipliers and use limited storage thereby leading to more economical hardware implementation. The register word length of the filter in each stage is carefully dimensioned in order to minimize the required hardware. Furthermore, the digital filters operate with a reduced supply voltage to 1.5V. Simulation results show that the modulator achieves the resolution higher than 12bits and 2.4mW power consumption per ADC at 7.7k Samples/s rate.
Time of flight laser range finding, deep space communications and scanning video imaging are three applications requiring very low noise optical receivers to achieve detection of fast and weak optical signal. HgCdTe electrons initiated avalanche photodiodes (e-APDs) in linear multiplication mode is the detector of choice thanks to its high quantum efficiency, high gain at low bias, high bandwidth and low noise factor. In this project, a readout integrated circuit of hybrid e-APD focal plane array (FPA) with 100um pitch for 3D-LADAR was designed for gated optical receiver. The ROIC works at 77K, including unit cell circuit, column-level circuit, timing control, bias circuit and output driver. The unit cell circuit is a key component, which consists of preamplifier, correlated double Sampling (CDS), bias circuit and timing control module. Specially, the preamplifier used the capacitor feedback transimpedance amplifier (CTIA) structure which has two capacitors to offer switchable capacitance for passive/active dual mode imaging. The main circuit of column-level circuit is a precision Multiply-by-Two circuit which is implemented by switched-capacitor circuit. Switched-capacitor circuit is quite suitable for the signal processing of readout integrated circuit (ROIC) due to the working characteristics. The output driver uses a simply unity-gain buffer. Because the signal is amplified in column-level circuit, the amplifier in unity-gain buffer uses a rail-rail amplifier. In active imaging mode, the integration time is 80ns. Integrating current from 200nA to 4uA, this circuit shows the nonlinearity is less than 1%. In passive imaging mode, the integration time is 150ns. Integrating current from 1nA to 20nA shows the nonlinearity less than 1%.
This paper presents a low power and small area analog-digital converter (ADC) for infrared focal plane arrays (IRFPA) readout integrated circuit (ROIC). Successive approximation register (SAR) ADC architecture is used in this IRFPA readout integrated circuit. Each column of the IRFPA shares one SAR ADC. The most important part is the three-level DAC. Compared to the previous design, this three-level DAC needs smaller area, has lower power, and more suitable for IRFPA ROIC. In this DAC, its most significant bit (MSB) sub-DAC uses charge scaling, while the least significant bit (LSB) sub-DAC uses voltage scaling. Where the MSB sub-DAC consists of a four-bit charge scaling DAC and a five-bit sub-charge scaling DAC. We need to put a scaling capacitor Cs between these two sub-DACs. Because of the small area, we have more design methods to make the ADC has a symmetrical structure and has higher accuracy. The ADC also needs a high resolution comparator. In this design the comparator uses three-stage operational amplifier structure to have a 77dB differential gain. As the IR focal plane readout circuit signal is stepped DC signal, the circuit design time without adding the sample and hold circuit, so we can use a DC signal instead of infrared focal plane readout circuit output analog signals to be simulated. The simulation result shows that the resolution of the ADC is 12 bit.
This paper presents a real-time processing system designed for infrared FPA. The real-time processing is a key technology in the infrared image processing system<sup></sup>. In this paper, the pre-processing and segmentation approaches are combined in order to achieve a good result from infrared images which have large noise, complex background and ambiguous target<sup></sup>. This design is a real-time IR image processing system based on Xilinx's VIRTEX-5, fully using of VIRTEX-5 FPGA’s high performing, the FPGA embedded Xilinx's MicroBlaze processor core, and high-performance pre-processing function modules. Data signals processed by FPA can be collected to carry out filtering calculation, and the LCD displays the image, user can control the system by touching screen real-time.
Ultra-low light imaging and passive/active dual mode imaging require very low noise optical receivers to achieve
detection of fast and weak optical signal. HgCdTe electrons initiated avalanche photodiodes (e-APDs) in linear
multiplication mode is the detector of choice thanks to its high quantum efficiency, high gain at low bias, high bandwidth
and low noise factor. In my work, a passive/active dual mode readout integrated circuit (ROIC) of e-APD focal plane
array (FPA) is designed. Unit cell circuit architecture of ROIC includes a capacitance feedback transimpedance amplifier
(CTIA) as preamplifier of ROIC, a high voltage protection module, a comparator, a Sample-Hold circuit module, and
output driver stage. There is a protection module in every unit cell circuit which can avoid ROIC to be damaged from
avalanche breakdown of some diodes of detector. Conventional 5V CMOS process is applied to implement the high
voltage protection with the small area rather than Laterally Diffused Metal Oxide Semiconductor (LDMOS) in high
voltage BCD process in the limited 100um×100um pitch area. In CTIA module, three integration capacitances are
included in the CTIA module, two of them are switchable to provide different well capacity and noise. Constraints such
as pixel area, stability and power lead us design toward a simple one-stage cascade operational transconductance
amplifier (OTA) as pre-amplifier. High voltage protection module can protect ROIC to be damaged because of
breakdown of some avalanche diodes.
Design of readout-integrated circuit(ROIC) with high frequency and low signal for 512×256 short wavelength(SW) inferred-focal-plane-arrays(IRFPAs) is presented. The ROIC with high performance in frame rate can integrate and read out the low signal. An analog signal chain, which contains CTIA, CDS module, amplifier of charge and complementary output stage, can satisfy the high frequency and low signal application. A reliable digital control structure of IRFPA ROIC is presented, with which the integral voltage of arbitrary contiguous or noncontiguous lines, rather than regular lines, can be selected to readout. The simulation and verification are completed both before and after completing the layout. The circuit’s structure and operation principle are analyzed under the environment of mix-signal, and the result shows that the output dynamic range is over 2.5V, the charge capacity is more than 1Me-, the frame rate is 250Hz, the linearity within useful dynamic range is above 99.9 percent.
HgCdTe electrons initiated avalanche photodiodes (e-APDs) in linear multiplication mode can be used for high speed applications such as active imaging. A readout integrated circuit of e-APD FPA is designed for dual mode passive/active imaging system. Unit cell circuit architecture of ROIC includes a high voltage protection module, a Sample-Hold circuit module, a comparator, output driver stage and a integrator module which includes a amplifier and three capacitors. Generally, APD FPA works at reversed bias such as 5V-15V in active imaging mode, and pixels’ dark currents increase exponentially as the reverse-bias voltage is increased. Some cells of ROIC may be short to high voltage because of avalanche breakdown of diodes. If there is no protection circuit, the whole ROIC would be burnt out. Thus a protection circuit module introduced in every ROIC cell circuit is necessary to make sure the rest units of ROIC can still work. Conventional 5V CMOS process is applied to implement the high voltage protection with the small area other than LDMOS in high voltage BCD process in the limited 100μm×100μm pitch area. In integrator module, three integration capacitors are included in the ROIC to provide switchable well capacity. One of them can be shared in two modes in order to save area. Constraints such as pixel area and power lead us design toward a simple one-stage cascade operational transconductance amplifier (OTA) as pre-amplifier which can avoid potential instability caused by inaccuracy of MOSFET Model at 77K.
High frequency readout-integrated circuit(ROIC) of 512×256 staring short wavelength(SW) infrared focal plane arrays(IRFPAs), focusing on high-frame rate output and noise suppression is implemented in this paper. The design of ROIC mentioned in it takes the previous version into account. The complete analog signal chain contains a novel input stage of capacitor feedback transimpedance amplifier(CTIA) preamplifier, a CDS (correlated double sampling) module, an amplifier of charge and complementary output stage. This ROIC is a full-custom flow integrated circuit design. The parasitic parameters are extracted once the layout is finished. Then the design is improved according to the result of post-layout simulation, which leads to the great improvements of the majority of parameters. The test and simulation results show that the output voltage range is 2.8V, the frame rate is 250Hz and the linearity within useful voltage range is above 99.1 percent, even when the temperature is 77K.
A readout integrated circuit (ROIC) for 320× 256 middle-wave and long-wave infrared focal plane arrays, is studied in this paper. This circuit operates in integrating-while-reading (IWR) mode with the frame rate higher than 100fps. A novel DI structure is used for signal acquisition of middle wave while BDI structure for long wave. It is common that trade-offs always exist between chip area and performances in integrated circuits design. In order to get high injection efficiency for BDI structure with small area, a four-transistor amplifier with a gain of 82dB is designed. The charge capacity of ROIC is also a key performance parameter when considering the noise and the large middle-wave and longwave photocurrent (up to 5nA and 100nA, respectively). A structure named double sharing capacitors (DSC) presented in this paper will be an effective solution to getting a large capacity in the limited 50 μm x 50 μm pitch area. DSC means that each integrating capacitor has two kinds of shares. One is between the integrating capacitor and another integrating capacitor which is in the adjacent pixel, and the other is between the integrating capacitor and the holding capacitor in the same pixel. By adopting the 0.35μm 2P4M mixed signal process, the DSC architecture can make the total effective charge capacity as high as 70Me- per pixel with 3V output range. According to the simulation results, this circuit works well under 5V power supply and achieves 2.5MHz data transmission rate, less than 0.1% nonlinearity. Its total power consumption is less than 110mW.
This paper presents a low power ADC for the 512*512 infrared focal plane arrays (IRFPA) readout integrated circuit(ROIC). The major structure, the working mode and the simulation result of the readout integrated circuit are shown in this paper. The power supply voltage of 0.35μm standard CMOS process is 3.3V in this design, and then the output range of the Direct Injection (DI) input circuit is reached 2V. Successive-approximation-register (SAR) ADC architecture is used in this readout integrated circuit. And each ADC is shared by one column of the IRFPA. This SAR ADC is made up of a 13-bit digital-analog converter (DAC), a high resolution comparator, and a digital control circuit. The most important part is the voltage-scaling and charge-scaling charge redistribution DAC. In this DAC, charge scaling with a capacitor ladder to determine the least significant bits is combined with voltage scaling with a resister ladder to determine the most significant bits. The comparator uses three-stage operational amplifier structure to get a 77dB differential gain. The Common-Mode input rang of the comparator is 1V to 3V, and minimum resolvable voltage difference is 0.3mV. This SAR ADC has some advantages, especially in low power and high speed. The simulation result shows that the resolution of the ADC is 12 bit and the conversion time of the ADC is 6.5μs, while the power of each ADC is as low as 300μW. Finally, this SAR ADC can satisfy the request of 512*512 IRFPAs ROIC with a 100Hz frame rate.
In this paper, a new design of readout integrated circuit application in short wave infrared is introduced.
An amplifier of one transistor is employed in the CTIA to reduce the area of the unit cell. The output
unit cell achieved CDS (correlated double sampling) and SH (sample and hold) is designed for public
use of a whole line, and is outside the array. A new digital control structure of IRFPA ROIC is
presented, with which the integral voltage of arbitrary contiguous or noncontiguous lines, rather than
regular lines, can be selected to readout. The structure of the circuitry and the operation principle are
analyzed, showing that the output dynamic range is over 2.5V, the cell capacity is more than 0.5Me<sup>-</sup> the
frame rate is 250Hz, and the linearity within working dynamic range is above 99.9 percent. This design
is going to be fabricated through Chartered 0.35um double-poly-four-metal (DPFM) process technique,
and the pixel occupies a 30um by 30um area.
In our study, we designed a 512×512 readout integrated circuit (ROIC) for N-on-P short wave infrared
(SWIR) detectors, which has the ability to operate with two capacitors for different input current levels
from very low background applications to daytime high illumination conditions. A buffered direct
injection (BDI) readout cell as input circuit provides a low input resistance, high injection efficiency,
and precise biasing voltage to the photodiode at low input currents. In order to reduce the noise of the
BDI readout cell, a high-performance single stage amplifier is devised, the gain of which reaches as
high as 50dB. The input MOSFET of the amplifier operates at sub-threshold region to keep the
photodiode at precise reverse bias and steady injection efficiency. At the same time, with the input
MOSFET at sub-threshold region, the current is smaller than at saturation region, and the power
dissipation is reduced to a low level. A sample and hold circuit is also part of the input unit cell
architecture, which allows the infrared focal plane array (IRFPA) to be operated in full frame snapshot
mode and rolling mode. To prevent the excess of total current of the ROIC, the reset time of every row
has a lag of one period compared to the previous row. The simulation results confirm these advantages.
With the 5.0V power supply, ROIC provides the output dynamic range over 2.5V, the well capacity
more than 1×10<sup>6</sup>e-, and the total power dissipation less than 120mW. The final chip is fabricated with
HHNEC 0.35um 1P4M process technology, and the pixel occupies a 30um×30um area. The Testing
results are coincide with the simulations of the circuit. With the detecting current varies from 30pA to
1nA, the linearity of BDI is 99%, and it can be operated at the temperatures below 77K.