In microelectronic device manufacturing, photosensitive organic insulators (POIs) are widely used during passivation steps to protect and preserve the chips from damage due to subsequent processes and from the external environment. To ensure high performance and to maintain chip quality, a well-controlled POI lithography process and corresponding defectivity monitoring are needed. In this work, we present an automated method developed by STMicroelectronics and KLA for POI defectivity and process control employing a KLA 8 Series inspection system with illumination in the visible range. The highly sensitive macro inspection tool with dedicated analysis approaches and solutions successfully enabled the detection of the principal defects of interest, the identification of defectivity root causes through automatic classification and review, and the evaluation of the layer thickness and uniformity through reflected intensity heatmaps. For several months, this protocol has been applied to the production environment, proving to be effective in detecting even small deviations from the standard process. Here, we present some promising results obtained with this strategy, highlighting the benefits in terms of rework reduction and improved equipment management.
Appropriate solutions for post-lithographic defect management and process tool control are fundamental to ensure better chip quality and yield maintenance through the reduction of wafers at risk. The increasing demand in terms of wafer production capacity and sensitivity requirements from the automotive, MEMS and Internet of Things markets is leading advanced legacy semiconductor fabs to challenge their conventional after-develop-inspection (ADI) paradigm. In this work, we present a high throughput photolithography step monitoring scheme, developed by STMicroelectronics and KLA, employing an 8 Series patterned wafer defect inspection system for wafer frontside inspection and review. Namely, we demonstrate the capacity to capture die level defects together with full wafer excursions with a significant level of sensitivity, as well as a beneficial impact on yield improvement and lithography cell control. Moreover, we propose fast and reliable methods for monitoring the pattern shift and mask check, enabling increased wafer sampling and faster rework decisions. Lastly, we show well-engineered on-tool classification solutions at inspection runtime for each defect detected, allowing for improved control with high purity and fully automatic wafer disposition. Besides inline monitoring, we also show the capacity to check process tool performance, to detect lithography excursions faster and more effectively and have a better understanding of defectivity root causes. Moreover, to ensure complete control over the full lithography process, we show after-cleaning-inspection capabilities alongside conventional ADI. In this work, we present the beneficial aspects of the adopted strategy in terms of capacity improvement and critical defect detection in the production line.
Analysis of hotspots is becoming more and more critical as we scale from node to node. To define true process windows at sub-14 nm technology nodes, often defect inspections are being included to weed out design weak spots (often referred to as hotspots). Defect inspection sub 28 nm nodes is a two pass process. Defect locations identified by optical inspection tools need to be reviewed by review-SEM’s to understand exactly which feature is failing in the region flagged by the optical tool. The images grabbed by the review-SEM tool are used for classification but rarely for quantification. The goal of this paper is to see if the thousands of review-SEM images which are existing can be used for quantification and further analysis. More specifically we address the SEM quantification problem with connected component analysis.
In order to optimize the time to market of the newest technology nodes and maximize their profitability, advanced semiconductor manufacturers need to adapt their yield enhancement strategies to their current development stage. During very early development, gross Defectivity at some critical process steps often makes it impractical to use broadband plasma or laser scanning micro-defect patterned wafer inspection techniques: such sensitive defect inspections capture a large number of defects, producing wafer defect maps so heavily populated that even wafer level signature are difficult to visualize.
The Liu-Nealey (LiNe) chemo-epitaxy Directed Self Assembly flow has been screened thoroughly in the past years in terms of defects. Various types of DSA specific defects have been identified and best known methods have been developed to be able to get sufficient S/N for defect inspection to help understand the root causes for the various defect types and to reduce the defect levels to prepare the process for high volume manufacturing. Within this process development, SEM-review and defect classification play a key role. This paper provides an overview of the challenges that DSA brings also in this metrology aspect and we will provide successful solutions in terms of making the automated defect review. In addition, a new Real Time Automated Defect Classification (RT-ADC) will be introduced that can save up to 90% in the time required for manual defect classification. This will enable a much larger sampling for defect review, resulting in a better understanding of signatures and behaviors of various DSA specific defect types, such as dislocations, 1-period bridges and line wiggling.
Optical bright field wafer inspection followed by repeater analysis is used to find a maximum number of programmed
and natural defects on a EUV patterned mask. Each aspect of the inspection methodology affecting the sensitivity of the
wafer inspection is optimized individually. A special focus is given to the wafer stack. Simulation is used to predict the
optimum stack properties and experimental verification is performed through exposures on the IMEC EUV Alpha Demo
Tool. The final result is benchmarked against state-of-the-art patterned mask inspection and blank inspection to evaluate
the capabilities and limitations of the optical wafer inspection. In addition, the locations obtained by each inspection
technique (wafer and mask) were reviewed on wafer by means of a new automated methodology that is based on a tight
stage accuracy of both inspection tool and review SEM.
After-develop inspection (ADI) and photo-cell monitoring (PM) are part of a comprehensive lithography process
monitoring strategy. Capturing defects of interest (DOI) in the lithography cell rather than at later process steps shortens
the cycle time and allows for wafer re-work, reducing overall cost and improving yield. Low contrast DOI and multiple
noise sources make litho inspection challenging. Broadband brightfield inspectors provide the highest sensitivity to litho
DOI and are traditionally used for ADI and PM. However, a darkfield imaging inspector has shown sufficient sensitivity
to litho DOI, providing a high-throughput option for litho defect monitoring. On the darkfield imaging inspector, a very
high sensitivity inspection is used in conjunction with advanced defect binning to detect pattern issues and other DOI
and minimize nuisance defects. For ADI, this darkfield inspection methodology enables the separation and tracking of
'color variation' defects that correlate directly to CD variations allowing a high-sampling monitor for focus excursions,
thereby reducing scanner re-qualification time. For PM, the darkfield imaging inspector provides sensitivity to critical
immersion litho defects at a lower cost-of-ownership. This paper describes litho monitoring methodologies developed
and implemented for flash devices for 65nm production and 45nm development using the darkfield imaging inspector.