The reduction of measurement data and the reduction of time required to select the sample plan are essential for the development of an efficient lithography process model. We have discussed the strengths and weaknesses of existing sample plan selection techniques and proposed a locally linear embedding (LLE)-based sample selection technique. The proposed approach significantly reduces the demand for metrology data and improves the modeling turn-around time without sacrificing the model accuracy and stability. The effectiveness of the proposed methodology is verified by modeling pattern transfer process of critical layers in 14- and 22-nm complementary metal–oxide–semiconductor technologies. The experimental results show that among different sample plan selection techniques, the LLE provides a competitive sample plan choice in a single shot without compromising the accuracy.
A two-stage approach is introduced to improve the accuracy of compact patterning models used in large-scale computational lithography. Each of the two stages uses a separate empirically calibrated regression model whose accuracy at predicting printed feature dimensions has been proven in the usual standalone (single stage) mode. For the first model stage, we choose an established regularized regression model of the kind that accounts for resist non-idealities by suitably modifying the pre-thresholded exposing dose pattern, with the model basis functions taking the form of modified convolutions of adjustable kernels with the optical image. A different class of regression model is used in the second stage, namely a model that accounts for resist non-idealities by making a pattern-dependent local adjustment in the develop threshold, with the model basis functions being characteristic traits of the image trace along feature cutlines. However, rather than applying this second model in the usual mode where it adjusts the develop threshold applied to the exposing optical image, we use it to adjust a threshold that is applied to the improved effective dose distribution provided by the first-stage model. The effectiveness of the proposed method is verified by modeling pattern transfer of critical layers in 14- and 22-nm complementary metal–oxide–semiconductor (CMOS) technology. In our experience, little accuracy improvement is gained by expanding the complexity of standard single-stage models beyond the level of empirically proven model forms. However, even in a basic implementation, inclusion of a second stage of modeling will in itself reduce RMS error by ∼45 % in our 14-nm example. Moreover, accuracy improvement is further boosted to ∼55 % by adopting a minimax strategy in which the model is conservatively regularized according to the worst-case outcome in cross-validation tests but is calibrated according to the best-case outcome.
As technology nodes continue to shrink, optical proximity correction (OPC) has become an integral part of mask design to improve the subwavelength printability. The success of lithography simulation to perform OPC on an entire chip relies heavily on the performance of lithography process models. Any small enhancement in the performance of process models can result in a valuable improvement in the yield. We propose a robust approach for lithography process model building. The proposed scheme uses the clustering algorithm for model building and thereby improves the accuracy and computational efficiency of lithography simulation. The effectiveness of the proposed method is verified by simulating some critical layers in 14- and 22-nm complementary metal oxide semiconductor technology nodes. Experimental results show that compared with a conventional approach, the proposed method reduces the simulation time by 50× with ∼5% improvement in accuracy.