KEYWORDS: Indium arsenide, Logic, Digital signal processing, Field programmable gate arrays, Fourier transforms, Switches, Interfaces, Microcontrollers, Very large scale integration, Binary data
A system-level implementation of FFT architecture for long data series is presented. It exploits opportunities provided by the newest Programmable System-on-Chips (PSoC) to perform such intensive algorithms. The proposed strategy relies on a balanced partitioning of computational e
ort between an embedded ARM processor and an on-purpose designed FFT module based on a Radix-2 algorithm. The external memories are used to accommodate the large amount of complex data and twiddle coefficients. The embedded controller is purposely programmed to allow the high-level management of the algorithm and the correct flow of data among peripherals, without need of extra control logic. The proposed architecture can be easily reconfigured, in order to change input data length. When implemented using a Microsemi A2F500 SmartFusion FPGA chip, it consumes approximately 61% of available logic resources to compute a 65536-point FFT.
KEYWORDS: Transistors, Amplifiers, Very large scale integration, Power supplies, Molybdenum, Manufacturing, Telecommunications, Logic, Capacitance, Electronics
Aggressive CMOS scaling results in significant increase of leakage current in MOS transistors manufactured in deep
submicron regime. Consequently low power SRAM design becomes an important criteria in design of VLSI circuits. In
this work, a new six transistor (6T) SRAM cell based on dual threshold voltage and dual power supply techniques, has
been proposed for low leakage SRAM design. The proposed cell has been compared to the conventional 6T-SRAM,
using the 65 nm technology. Compared to conventional six transistor (6T) SRAM cell, new 6T SRAM cell reduces
leakage power consumption by 72.6%. Furthermore, the proposed SRAM cell shows no area overhead and comparable
read/ writes speed as compared to conventional 6T SRAM cell.
With aggressive scaling, one of the major barriers that CMOS technology faces is the increasing process variations. The
variations in process parameters not only affect the performance of the devices but also degrade the parametric yield of
the circuits. Adaptive repairing techniques like adaptive body bias were proved to be effective to mitigate variations in
the process parameters. In this paper, we evaluate the use of zone based self-repairing techniques to mitigate the impact
of process variations on SRAM cells. Two different techniques were experimented and analyzed through extensive
Monte Carlo simulations and exploiting a commercial 65nm technology. Obtained results demonstrate that
improvements up to 35.7% in variability factor for leakage power and up to 22.3% in Design Margin for leakage power
can be achieved by using the suggested approach.
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