Although maskless electron beam lithography is viewed as an alternative lithographic technology by the mainstream
semiconductor industry, it has long been a key lithographic tool of the compound semiconductor devices. It combines
very high resolution with a high depth of field, but its wide acceptance in semiconductor production has been hindered
by lower throughput when compared to optical lithography. Several new approaches to parallel e-beam lithography are
currently being developed. These technologies, however, have not yet demonstrated the throughput per dollar invested
that the current optical tools achieve. Given the cost and high throughput requirements set by most semiconductor
manufacturers, the new parallel e-beam lithography tools are likely to be used for processing only a few critical layers,
similar to the way the older electron beam tools are used by compound semiconductor manufacturers. Overlay accuracy
is another big challenge when mixing optical and E-beam lithography tools. An alignment mark strategy is needed
which will results in optimum registration accuracy between E-beam and optically defined layers on the chip.
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