For the high volume manufacturing at the 45nm node and beyond it is crucial to match the OPC behaviour
of all scanners used at a given process step. For this task the ASML LithoTuner PatternMatcher software was
used. LithoTuner PatternMatcher is a tool to improve the proximity differences between a reference
scanner and one or more so called 'to be matched' scanners. The optimization uses the concept of
sensitivities of CDs of critical features towards adjustable scanner parameters in combination with the delta
CD's of those critical features.
To perform the scanner matching it is very important to have accurate and repeatable CD data. Therefore
we investigated the use of scatterometry as a replacement for the traditional CDSEM measurement.
Scatterometry significantly enhances the measurement precision while simultaneously reduces the
measurement time. In a first step we determined the sensitivities of the structures by measuring the CD
response to small perturbations of the individual scanner parameter settings. CD through pitch and
repeating 2 dimensional line end structures were measured using the ASML YieldStar tool and a Hitachi
CDSEM. The scatterometry- and CDSEM based sensitivities of the scanner parameter settings are compared.
Finally a scanner matching based on both sets of sensitivities has been performed.
In this article we will show that both methods are suited to perform the scanner matching. We will also
present the differences between the two sets of sensitivities obtained with scatterometry and CDSEM. At
the end we will present the results of the tool matching and show the results of a cross check. In the cross
check sensitivities obtained with the use of scatterometry were used for the scanner matching next to SEM
metrology used for verification.
Differences in imaging behaviour between lithographic systems of the same wavelength result in variations of optical
proximity effects (OPE). A way to compensate these irregularities is through scanner tuning. In scanner tuning, scanner
specific adjustments are obtained through the determination of scanner knob sensitivities of relevant structures followed
by an optimization to adjust the structure CD values to be close to the desired values.
Traditionally, scanner tuning methods have relied heavily on wafer-based CD metrology to characterize both the initial
mismatch as well as the sensitivities of CDs to the scanner tuning knobs. These methods have proven very successful in
reducing the mismatch, but their deployment in manufacturing has been hampered by the metrology effort. In this paper,
we explore the possibility of using ASML's LithoTuner PatternMatcher FullChip (PMFC) computational lithography
tool to reduce the dependence on wafer CD metrology.
One tuning application using flexray illumination instead of traditional scanner knobs is presented in this work; in this
application individual critical features in wafer printing are improved without affecting other sites. The limited impact of
tuning on other structures is verified through full-chip LMC runs. Potential uses of this technology are for process
transfers from one fab to another where the OPC signature in the receiving fab is similar but not identical to the signature
of the originating fab.
The tuning application is investigated with respect to its applicability in a production environment, including further
metrology effort reduction by using scatterometry tools.
As optical lithography pushes towards the 32nm node and as the k<sub>1</sub> factor moves toward 0.25, scanner performance and
operational stability are the key enablers to meet device scaling requirements. Achieving these requirements in
production requires stable lithography tools and processes. Stable performance is tracked with respect to pattern to
pattern overlay, nominal focus and critical dimension uniformity (CDU). Within our paper we will characterize the
intrinsic lithographic performance of the scanner and will discuss a new method of machine control to improve the
stability and thus the overall performance of the lithographic solution. This is achieved by measuring specific monitor
wafers, modeling the results by a new software algorithm and constantly feeding back corrective terms to the scanner.
Diffraction-based optical dimensional scatterometry was selected because of its precision, its ability to measure overlay
and focus with a single metrology recipe and its capability to generate greater amounts of measurement data in a shorter
time period than other metrology techniques and platforms.
While monitor wafer performance can be indicative, we will discuss the impact of the new control loop on product. We
will take a closer look at possible interactions with the existing process control loops and work through the configuration
of both internal and fab control loops. We will show improvements in the focus performance on product wafers by using
scatterometry as well. Most importantly we will demonstrate that the newly implemented control loop resulted in a
significant improvement of the CD and overlay performance of critical product layers. This had a very positive impact
on overall process variation and the rework rate at lithography.
As the semiconductor industry moves to 3X technology nodes and below, holistic lithography source mask
optimization (SMO) methodology targets an increase in the overall litho performance with improved process windows.
The typical complexity of both mask and illumination source exceeds what the lithographic industry has been
accustomed to, and presents a novel challenge to mask qualification and metrology. In this paper we demonstrate the
latest in aerial imaging technologies of Applied Material's Aera2<sup>TM</sup> mask inspection tool. The aerial imaging
capability opens the door to a wide variety of metrological measurements analysis at aerial level and provides enabling
solutions for mask and scanner qualifications. In particular, we demonstrate core and periphery DRAM pattern process window assessment and MEEF measurements, performed on an advanced test mask.
The extension of ArF lithography through reduced k1, immersion and double patterning techniques makes lithography a
difficult challenge. Currently, the concept of simple linear flow from design to functional photo-mask is being replaced
by a more complex scheme of feedback and feed-forward loops which have become part of a complex computational
lithography scheme. One such novel lithography concept, called "holistic lithography", was recently introduced by
ASML, as a scheme that makes the lithography process a highly efficient solution for the scaled down geometries. This
approach encourages efficient utilization of computational lithography and the use of feed-forward and feed-back critical
dimension (CD) and overlay correction loops. As sub-nanometer feature dimensions are reached for 3x nodes, with k1
reaching the optics limitations, Mask error enhancement factor (MEEF) values grow fast, thus making mask uniformity
fingerprint and degradation throughout its life time a significant factor in printed CDU on the wafer. Whereas the
consensus is on the need for growing density of intra-field data, traditional critical dimension scanning electron
microscope (CDSEM) Feed backward loops to the litho-cell become unsuitable due to the high density CD measurement
requirements. Earlier publications proposed implementing the core of the holistic lithography concept by combining two
technologies: Applied Material's IntenCD<sup>TM</sup> and ASML DoseMapper . IntenCD metrology data is streamed in a feedforward
fashion through DoseMapper and into the scanner, to create a dose compensation recipe which improves the
overall CDU performance. It has been demonstrated that the IntenCD maps can be used to efficiently reduce intra-field
printed CDU on printed wafers.
In this paper we study the integration concept of IntenCD and DoseMapper in a production environment. We implement
the feed-forward concept by feeding IntenCD inspection data into DoseMapper that is connected to ASML's
TWSINCAN<sup>TM</sup> XT:1900i scanner. We apply this concept on printed wafers and demonstrate significant reduction in
intra-field CDU. This concept can effectively replace the feedback concept using send-ahead wafers and extensive
CDSEM measurements. The result is a significant cost saving and fab productivity improvement. By routinely
monitoring mask-based CDU, we propose that all photo-induced transmission degradation effects can be compensated
through the same mechanism. The result would be longer intervals between cleans, improved mask lifetime, and better
end of line device yield.
The tight process window of advanced lithography in the semiconductor industry is further challenged by
the growing contribution of photo-mask related CD variations. In previous technology generations,
global measurement and global correction were sufficient to compensate for critical dimension uniformity
(CDU) variations deriving from various sources. However, in the low K<sub>1</sub> regime for 45nm nodes and
below, cross-coupled effects such as Mask Error Enhancement Factor (MEEF) and mask CDU can easily
consume the overall CD budget related to lithographic process steps (see table 3).
ASML's DoseMapper was designed to correct system (e.g. scanner, track) and non-system (e.g. mask)
related errors controlled by an Automated Process Control (APC) system. It was introduced as a
method for correcting intra-field and inter-field variations, relying on feedback from printed wafer based
metrology. Here we propose using AMAT's IntenCD<sup>TM</sup> map for supplying dense CDU measurement
results from the reticle as a feed-forward input to DoseMapper. The IntenCD<sup>TM</sup> application characterizes
CD uniformity of 'features of interest' across the mask in the form of a dense map with high accuracy and
The case studies presented in this paper are the result of collaboration between AMAT and ASML to
demonstrate the benefit of feeding IntenCD output into DoseMapper CD analyzer which translates the
mask CD map into a scanner dose recipe.
The integrated solution can be implemented in manufacturing factories to shorten turnaround time and
improve the exposure process window. It can be used to compensate for CDU effects due to mask
production as well as contributions due to life time deterioration.
In this paper, the intra-field critical dimension (CD) control of a KrF step&scan and step&repeat system are investigated and compared. The scanners are expected to replace the conventional steppers in the manufacturing of integrated circuit generation of 0.18 micrometer and beyond, because of the larger field size and the intrinsic improvement in intra- field CD and overlay control using comparable lens design, complexity and cost. The work has been focused on sub-0.25 micrometer critical dimensions. A reticle design for both top- down CD measurements and electrical linewidth probing has allowed massive data collection and investigation of the impact of the metrology technique in CD control studies. From this study, it can be concluded that the stepper and scanner exhibit similar CD control at best focus, but the scanner improves the CD control of the stepper if the considered focus range increases. The CD control is governed by the reticle CD non-uniformity. Focus budget calculations indicate that reticle CD ranges of 40 nm (4x) are needed to bring the CD control of 0.2 micrometer grouped lines within acceptable ranges for realistic gate levels. For isolated lines, dedicated deep-UV resists and resolution enhancement techniques will be needed on top of this to obtain similar CD control.
The push to achieve higher density devices continues to place tremendous demands on optical lithography. Several techniques have been used to achieve 0.35 micrometers feature sizes. This paper presents data on the practical application of numerical aperture (NA) and partial (sigma) for 0.35 micrometers imaging. A number of conventional photoresist systems are characterized at various NA/(sigma) . Important differences in the response of photoresists have been observed. These are quantified with respect to various types of structures. Of particular interest are the affects on dense lines and contact structures. The affect of bias also is quantified by using a special reticle where pitch is held constant and the chrome linewidth is varied to determine optimal process latitude. After examining the imaging performance of a few high-contrast photoresists, the use of normalized image log-slope (NILS) is applied for two stepper conditions. Finally, response curves are generated to show optimal exposure conditions for resolution and depth of focus versus NA/(sigma) performance for a number of different NILS photoresists.
The performance of off-axis illumination techniques in comparison to conventional illumination has been investigated for features in the 0.5*((lambda) /NA) range. Conventional masks, chromium masks with assistant features, and halftone phase-shifting masks have been used in combination with these techniques. The analysis includes dense and isolated test features as well as real design features of a random logic IC. Advanced positive tone i-line resists and a 0.48 NA wafer stepper have been applied. Focus and exposure latitudes, linearity, cd proximity effects, and feature deformations caused by the applied techniques are considered. The analysis is done experimentally and theoretically based on cd calculations of developed resist features using Depict-3. The advantages and drawbacks of these techniques are discussed. An ultimate resolution of dense IC features down to 0.30 micrometers for a 0.48 NA i-line wafer stepper is achieved using annular illumination with halftone phase-shifting masks. For 0.5*((lambda) /NA) features practically usable latitudes are demonstrated.
Trends in optical lithography lead to 0.35 micrometers resolution as being the next critical linewidth for semiconductor production. The 64 Mb DRAM technologies will require this. Current i-line lithography techniques lack sufficient production tolerance for 0.35 micrometers . To achieve greater depth of focus and exposure latitude, a number of new techniques are being explored. These include phase shifting masks, multiple focal plane exposures, surface imaging, DUV lithography as well as off-axis illumination. This paper examines the contribution of off-axis illumination towards the improvement of process latitude. Experimental data using 0.54 and 0.48 NA lenses are presented showing the relative advantages and disadvantages of this technique. This data is evaluated for its potential production use for 0.35 micrometers lithography. The effect of off-axis illumination is evaluated for isolated lines, dense lines, sagittal/tangential lines, and contact features. To examine thin film effects, a number of commercially available photoresist processes are used for these tests. In addition, novel solutions to limitations encountered with off-axis illumination are modeled and experimentally verified.
Many lithographic approaches to achieving 0.35 micron IC design rules have been proposed. Several years ago, the primary candidate was x-ray lithography. Today it is generally acknowledged that an optical approach will be used for such design rules. Both deep UV and i-line stepper technologies have progressed with capability to achieve 0.35pm design rules. High NA, wide-field lenses now exist for both deep UV and i-line , With the renewed interest in phase shift technology, i-line capability at 0.35pm design rules is comparable to deep UV technology.
The development of a stepper architecture that allows both wide-field i-line and deep UV lenses to be accommodated in the same body and using thru-the-lens, direct-reticle-referenced alignment method  is reported. Common improvements in the areas of stage, die-by-die leveling and environmental control allow exceptional overlay performance to be achieved for both i-line and deep UV. The use of common architecture and the same alignment method facilitates the optimum mix and match combination of i-line and deep UV at
0. 35?m design rules
Experimental investigation of stepper performance is reported in comparison to criteria established for design rules at 0.35pm. Overlay is evaluated on substrates typical of CMOS IC manufacturing. Lithographic performance is investigated using conventional techniques as well as more advanced techniques including phase shift reticles.
Results indicate that overlay performance on tested substrates meets the requirements for 0.35?m design rules. Lithographic results indicate that 0.35pm lines/spaces are achievable using both conventional i-line and deep UV techniques, however, the implementation of phase shift reticles enhances the process latitudes for i-line at 0.35?m.
Shipley XP-89131 is a wet developable negative tone DUV resist, capable of resolving features down to 0.3 micrometers when used in conjunction with the ASM- L PAS 5000/70 stepper (NA equals 0.42). Practical implementation of this material at the limit, however, is marred by several problems, notably, poor C.D. (critical dimension) control over steps, inadequate adhesion and the formation of various types of residue between features. The authors have endeavored to find means by which these effects may be reduced. Methods investigated for tackling the residue problem have included the use of metal ion free and metal ion containing developers, a comparison of puddle, immersion and spray develop processes, changes in the percentage overdevelopment employed, as well as the effect of developer temperature. Additional work has been directed towards examining the effect of post-exposure baking time. The high transparency of such resists, coupled to the high reflectivity of substrates at 248 nm, gives rise to severe C.D. control problems over topography. We examine the effectiveness and tradeoffs of two alternative approaches potentially capable of effecting an improvement. Spin coatable DUV ARC materials have been found to significantly improve C.D. control over polysilicon and aluminum topography, although the more retrograde profiles observed, in conjunction with optical proximity effects, can impose other limitations. Several beneficial side effects have been noted, however, including improved adhesion on aluminum substrates, a wider exposure window and easier stripping of the resist following dry etching. Potential yield reducing factors such as the presence of resist residues or bridges between features, are also significantly reduced during the dry development of the ARC. The alternative method of employing dyed resists has also been evaluated using both Shipley XP-90166 and XP-90174 resists. While the latter version does offer some improvements over the undyed XP-89131 material, it is not as effective as the ARC approach in controlling C.D.s over topography. It is apparent too that the resolution limit of such materials has been blunted. Finally the focus and exposure latitude has been determined for features printed on silicon, both with and without ARC. In a similar way the focus/exposure window has been determined for etched contacts.
i-line wafer steppers have become the tool of choice for submicron production of advanced integrated circuits. These tools are now being extended to provide the required resolution, linewidth control, and overlay performance for devices with 16 Mb packing densities. To achieve this a manufacturing environment, suitable control procedures should be designed to minimize process and equipment variations. The primary goal of this paper is to characterize and quantify the ability of current generation steppers to meet or exceed the 100 nm AA (single machine) and the 175 nm BC (stepper to any other stepper in a production area) overlay requirements for half-micron production. For this, an overlay experiment using one reference and 12 randomly selected steppers was performed. Two Point through the lens alignment was used to reference wafer to reticle. Stages with three interferometrically controlled axes having both standard and enhanced resolution were used in the experiment. Features to improve stage positioning and overlay accuracy are discussed. To generate the required data, accurately calibrated reference wafers are used. The results were compared with a metrology model, which was used to optimize the matching of stepper lens and stage grid distortions so that optimum matching performance is achieved. The results then clearly predict whether all steppers meet the stringent overlay requirements for half-micron lithography in a production environment. In addition, experimental results show half-micron resolution performance with a number of commercially available i-line photoresists. Lens performance as affected by a phase-shifted reticle tooling are also examined to determine its potential benefit to 0.5 micron and sub-0.5 micron production.