The ability to control critical dimensions of structures on semiconductor devices is paramount to improving die yield and device performance. Historical methods of controlling critical dimensions include; tool matching, limiting processes to a limited tool set, and extensive monitoring. These methods have proven reasonably effective in controlling critical dimensions, but they are labor and resource intensive. The next level of factory performance is to automate corrections and drive critical dimensions to target. Use of this type of control, commonly referred to as Advanced Process Control (APC) has been a trend that is increasingly becoming the norm in our industry. This paper outlines the implementation of a controller that effectively targets Final Inspection Critical Dimensions (FICD's). This is accomplished by feeding Develop Inspection Critical Dimensions (DICD), FICD, chip code and chamber information in to a model. The controller makes use of a model to make recommendations for recipe parameters. These recipe parameters are transferred to the tool using XML protocol in an automated fashion. Offsets and disturbances are effectively adjusted for. This controller has been implemented in a production facility and has resulted in a 70 % improvement in Cpk performance.
Proc. SPIE. 5755, Data Analysis and Modeling for Process Control II
KEYWORDS: Signal to noise ratio, Statistical analysis, Detection and tracking algorithms, Sensors, Manufacturing, Inspection, Monte Carlo methods, Semiconductor manufacturing, Algorithm development, Semiconducting wafers
In-line measurements are used to monitor semiconductor manufacturing processes for excessive variation using statistical process control (SPC) chart techniques. Systematic spatial wafer variation often occurs in a recognizable pattern across the wafer that is characteristic of a particular manufacturing step. Visualization tools are used to associate these patterns with specific
manufacturing steps preceding the measurement. Acquiring the measurements is an expensive and slow process. The number of sites measured on a wafer must be minimized while still providing sufficient data to monitor the process. We address two key challenges to effective wafer-level monitoring. The first challenge is to select a small sample of inspection sites that maximize detection sensitivity to the patterns of interest, while minimizing the confounding effects of other types of wafer variation. The second challenge is to develop a detection algorithm that maximizes sensitivity to the patterns of interest without exceeding a user-specified false positive rate. We propose new sampling and detection methods. Both methods are based on a linear regression model with distinct and orthogonal components. The model is flexible enough to include many types of systematic spatial variation across the wafer. Because the components are orthogonal, the degree of each type of
variation can be estimated and detected independently with very few samples. A formal hypothesis test can then be used to determine whether specific patterns are present. This approach enables one to determine the sensitivity of a sample plan to patterns of interest and the minimum number of measurements necessary to adequately monitor the process.
The oxide etch rate of a single chamber of plasma etch tool is estimated from plasma impedance data collected during the etch process. The etch rate is estimated using a linear statistical model and etch rate measurements performed on special test wafers. Stepwise regression is used to select possible predictors from a large pool of summary statistics calculated from the plasma impedance waveforms. The relationship of the estimated mean etch rate to yield and potential yield optimization is explored. An example application of an
advanced process controller to optimize the yield of the wafers processed by the etch tool in the presence of varying chamber conditions is also presented.
The ability to control critical dimensions of structures on semiconductor devices is paramount to improving die yield and device performance. Historical methods of in-line metrology, Scanning Electron Microscopes (SEM), ellipsometry, and scatterometry give the ability to monitor critical dimensions and film thickness. These methods, with some challenges on smaller technology nodes, have proven effective in identification of changes critical measurements. They let you know that something has changed. The next step in factory performance is to improve the ability to quickly identify the root cause of the variation and to address it to minimize the impact on revenue. Our focus has been on some novel means of characterizing tool performance. In this paper, we outline our methods of system fingerprinting of real-time temperature measurements. This trace represents what the wafer is subjected to during normal processing. Trough periodic monitoring we are able to determine if the efficacy of conductance between the plasma and the chuck is normal. In addition, when variations in down stream measurements (CD’s and film thickness) arise, we are able to quickly identify if our production tools are operation normally. If there are abnormalities in the tool performance, we are able to quickly identify where and when the problem is taking place. The real time aspect of monitoring plasma on temperature is an added level of resolution that aids in trouble shooting tool performance.
The ability to control critical dimensions of structures on semiconductor devices is essential to improving die yield and device performance. As geometries shrink, accuracy of the metrology equipment has increasingly become a contributing factor to the inability to detect shifts which result in yield loss. Scatterometry provides optical measurement that better enables process control of critical dimensions. Superior precision, accuracy, and higher throughput can be achieved more cost effectively through the use of this technology in production facilities.
This paper outlines the implementation of Scatterometry based metrology in a production facility. The accuracy advantage it has over conventional Scanning Electron Microscope (SEM) measurement is presented. The Scatterometry tool used has demonstrated repeatability on the order of 3σ < 1 nm at STI-Etch-FICD for CD and Trench Depth (TD), and Side Wall Angle (SWA) measurements to within 0.1 degrees. Poly CD also shows 3σ < 1 nm, and poly thickness measurement 3σ < 2.5 Å.
Scatterometry has capabilities which include measurement of CD, structure height and trench depth, Sidewall angle (SWA), and film thickness. The greater accuracy and the addition of in-situ Trench depth and sidewall angle have provided new measurement capabilities.
There are inherent difficulties in implementing scatterometry in production wafer fabs. Difficulties with photo resist measurements, film characterization and stack set-up will be discussed. In addition, there are challenges due to the quantity data generated, in how to organize and store this data effectively. A comparison of the advantages and shortcomings of the method are presented.