In this paper, the frequency response of a VLSI compatible Si-CMOS p-i-n photodetector suitable for high-speed, lowvoltage
operation is studied. The model is developed considering the effects of diffusion of carriers from the substrate
region and the parasitic elements due to the presence of multiple diodes in lateral configuration. The current density is
calculated considering square-area photodetector. Results indicate the possibility of optimum designs to maximize 3dB
bandwidth.
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