Inverse mask synthesis, or Inverse Lithography Technology, as a next generation resolution enhancement technology,
is drawing pretty much attention after years of development. However, the existing optimized mask usually
is too complex such that the pattern simplifying procedures have to be applied as a post processing step. But
the post processing step may lead to pattern degradation and unwanted side lobe printing. In this paper, we
first implement a new inverse mask synthesis system using two dimensional discrete cosine transform(DCT2)
of the target mask, where the low frequency components are used in the optimization. As the high frequency
components are discarded, the resulted optimal pattern is similar in shape to that of using the level set method
in the published papers. Moreover, as inverse mask synthesis is an ill-posed problem, there are some local minimum
locations. Previous algorithms usually use the desired pattern as an initial iteration point, in the sense
that optimized pattern shall be a perturbation of the desired pattern. A common fact is that initial solution
is critical to the optimization procedure and final result. In this paper, we apply an initial SRAF insertion
around the main features before starting the existing inverse engine. The SRAF insertion does not need to be
as accurate as that in the traditional SRAF+main feature OPC flow. Therefore, it does not add higher time
burden on the whole mask synthesis flow. We implement the SRAF insertion based on computed mask electric
field distribution. The experimental results show that using the initial fast SRAF insertion, the inverse engine
is able to take advantage of a better initial high contrast image distribution, and the optimized pattern can be
much simpler while the pattern fidelity is still in good control. We also observe that better optimized patterns
can be achieved with fewer iterations.
Optical proximity correction (OPC) is one of the most widely used resolution enhancement techniques (RET) in nanometer designs to improve subwavelength printability. Conventional model-based OPC assumes nominal process conditions without considering process variations because of the lack of variational lithography models. A simple method to improve OPC results under process variations is to sample multiple process conditions across the process window, which requires long run times. We derive a variational lithography model (VLIM) that can simulate across the process window without much run-time overhead compared to the conventional lithography models. To match the model to experimental data, we demonstrate a VLIM calibration method. The calibrated model has accuracy comparable to nonvariational models, but has the advantage of taking process variations into consideration. We introduce the variational edge placement error (VEPE) metrics based on the model, a natural extension to the edge placement error (EPE) used in conventional OPC algorithms. A true process-variation aware OPC (PVOPC) framework is proposed used the VEPE metric. Due to the analytical nature of VLIM, our PVOPC is only about 2 to 3× slower than the conventional OPC, but it explicitly considers the two main sources of process variations (exposure dose and focus variations) during OPC. Thus our post-PVOPC results are much more robust than the conventional OPC ones, in terms of both geometric printability and electrical characterization under process variations.
Yield is one of the most important factors for massive semiconductor circuits production. As process variation tolerances
decrease and the number of contacts/vias increase in modern technologies, contact/via failure has increased substantially,
which attracts many attentions from both manufacture and design domains. Among all the contact/via failure mechanisms,
lithography related ones become more important, the majority of which are rooted in focus and dose variations. Since the
lithography image robustness is pattern dependent, conventional design rules are becoming less efficient and effective to
convey the information. Models should be established to facilitate the evaluation of the lithography pattern robustness.
Meanwhile, the models need to be fast enough to be used in design tools. Since Optical Proximity Correction (OPC) is
very expensive to apply, the metric should be computed without doing actual OPC. We develop two new pre-OPC metrics
to predict the post-OPC contact/via CD error due to focus variation, which are validated by our simulations. However, the
metric for the post-OPC contact/via CD error due to dose variation is found not correlated well to the actual simulation.
Further investigation is needed to increase the metric accuracy.
In 90nm technology and beyond, process variations should be considered such that the design will be robust with respect to process variations. Focus error and exposure dose variations are the two most important lithography process variations. In a simple approximation, the critical dimension (CD) is about linearly related to the exposure dose variation, while it is quadratically related to the focus variation. Other kinds of variations can be reduced to these variations effectively as long as they are small. As a metric to measure the effects of exposure dose variations, normalized image log-slope (NILS) is pretty fast to compute once we have the aerial images. OPC software has used it as an optimization objective. But focus variation has not been commonly considered in current OPC software. One way is to compute several aerial images at different defocus conditions, but this approach is very time consuming. In this paper, we derive an analytical formula to compute the aerial image under any defocus condition. This method works for any illumination scheme and is applicable to both binary and phase shift masks (PSM). A model calibration method is also provided. It is demonstrated that there is only about 2-3x runtime increase using our fast focus-variational lithography simulation compared to the current single-focus lithography simulation. To confirm the accuracy, our model is compared with PROLITH<sup>TM</sup>. This ultra-fast simulator can enable better and faster process-variation aware OPC to make layouts more robust under process variations, and directly guide litho-aware layout optimizations.