This paper reviews current piezo-resistive characteristics pertaining to conventional and novel piezo-resistive strain transducers. These characteristics govern the performance of the sensor node. In this application, low power consumption, high signal to noise ratio (SNR), sensitivity and resolution in the sensor node are optimized for a distributed sensor network. In this low frequency application at < 100 Hz, it is found that electrical noise can limit the nominal resistance of the strain gauge to be used. By reducing the nominal resistance to lower the SNR, power consumption is increased. Optimization of the nominal resistance for excess noise and other material parameters must take place. Typical values have been used to explore the SNR over a range of resistance values and against frequency. The trade-off is also optimized in the volume and sheet resistance of the piezo-resistive material. Irreversible phenomena such as ageing and material creep are responsible for very low frequency drift (approaching DC) with respect to time and temperature. It is found that this drift is material specific and can be numerically compensated in situ. Maximizing sensitivity of the transducer is desirable to reduce the overhead at the sensor front-end. This overhead is shown to be dependant on gauge factor and the configuration of the strain-sensing circuit. The configuration of the strain-sensing circuit impacts on cost, complexity and SNR.
The ultimate goal of micro-systems is ad hoc arrays of wireless, self powered intelligent sensors which self-assemble on installation and adjust to a changing number of sensors and/or changing sensor location. The sensors and the network infrastructure must be low cost, disposable (recyclable), unobtrusive and these ultimate goals impact on all aspects of sensor design and network protocols. In this paper, a number of strategies employed to achieve these goals are outlined. In particular, some recent technological developments have facilitated more efficient sensor networks. These include smart antennas, low power electronics and sensors, creative methods of data reduction and "tipping bucket" data streaming. Sensor networks with lifetimes of more than one year are now possible.
Current methods used to study neural communication have not been able to achieve both good spatial and temporal resolution of recordings. There are two ways to record synaptic potentials from nerve endings: recordings using single or dual intracellular or extra cellular metal electrodes give good temporal resolution but poor spatial resolution, and recording activity with fluorescent dyes gives good spatial resolution but poor temporal resolution. Such medical research activity in the area of neurological signal detection has thus identified a requirement for the design of a CMOS circuit that contains an array of independent sensors. As both spatial and temporal distribution of acquired data is required in this application, the circuit must be capable of continuous measurement of synaptic potentials from an array of points on a tissue sample, with a 10 μm separation between sensor points.
The major requirement for the circuit is that it is capable of sensing synaptic potentials of the order of several mV, with a resolution of 0.05 mV. For data recording purposes, the circuit must amplify these synaptic potentials and digitise them together with their locations in the sensor array. Finally, the circuit must be biologically inert, to avoid specimen deterioration.
This paper presents the design of a prototype single-chip circuit, which provides a 6 x 3 array of independent synaptic potential sensors. The signal from each of the sensors is amplified and time-multiplexed into an on-chip A/D converter. The circuit provides an 8-bit synaptic potential value, together with an 8-bit field containing array location and trigger signals suitable for external data acquisition instrumentation.
Our test circuit is implemented in a low-cost 0.5 um, 5 V CMOS process. The fabricated die is mounted in a standard 40 pin DIP ceramic package, with no lid to allow direct contact of the die surface with the tissue sample. The only post-processing step required for these packages is to encapsulate the exposed bond wires to ensure that the device is biologically inert. No further processing of the silicon die is required. Both the circuit design and the chip performance will be presented in the seminar.
The performance of low noise amplifiers (LNAs) is limited by the quality factors of the inductors used. Realizing fully integrated LNAs and other radio frequency (RF) circuits requires the development of techniques to improve the quality factors of on-chip inductors. It was found that the maximum attainable tank-Q of on-chip square spiral inductors for a given technology remained fairly constant and independent of the number of turns and the width of the tracks. Based on this on-chip spiral inductors were designed for applications in resonant tank circuits. A 433 MHz Industrial, Scientific and Medical (ISM) band tank circuit was designed based on a single spiral structure with a self-resonant frequency of 433 MHz, resulting in a decrease of 3.6% in the tank-Q compared to a circuit designed for maximum tank-Q. An LNA for a wireless receiver utilising a similar structure for the tuned load has been designed with a gain of 43 dB and a bandwidth of 1.74 MHz occupying an area of 0.48 mm2.