This paper describes the use of an FPGA based prototype to enable the rapid prototyping of IEEE 802.11 modems. Prototyping ASICs on a reconfigurable platform enabled concurrent development by the hardware and software teams, and provided a high degree of confidence in the designs. The capabilities of modern FPGAs and their development tools allowed easy and quick retargetting of the complex ASICs into FPGAs, enabling the integration of the prototyping effort into the design flow from the start of the project. The effect was to accelerate the development cycle and generate an ASIC which had been through one pass of beta testing before tape-out.
A 0.13um CMOS mixed signal 802.11a/b/g baseband PHY IC, with per-packet receive diversity, 802.11h radar/DFS support and an MRC/MIMO coprocessor interface, is described. Required receive C/N is 5dB at 6 Mbps, and 20dB at 54 Mbps. Residual packet error rate is less than 4% for 54 Mbps and 0.1% for 6 Mbps link data rates in a 50ns delay spread channel. The 4.75×4.75mm chip, fabricated in 1P7M 0.13um CMOS, has 8M transistors and dissipates under 31mW in sleep, 206mW in Tx, and 362mW in Rx.