Advancing technology nodes in DRAM continues to drive the reduction of on-product overlay (OV) budget. This gives rise to the need for OV metrology with greater accuracy. However, the ever increasing process complexity brings additional challenges related to metrology target deformation, which could contribute to a metrology error. Typically, an accurate OV measurement involves several engineering cycles for target and recipe optimization. In particular, process optimization in either technology development (TD) phase or high volume manufacturing (HVM) phase might influence metrology performance, which requires re-optimization. Therefore, a comprehensive solution providing accuracy and process robustness hereby minimizing the cycle time is highly desirable. In this work, we report multi-wavelength μDBO enhanced with accuracy aware pixel selection as a solution for robust OV measurement against process changes as well as improved accuracy in HVM. Accuracy aware pixel selection is capable of tackling intra-target processing variations and is established on a multi-wavelength algorithm with immunity to target asymmetry impact. DRAM use cases in FEOL critical layers will be discussed in this paper. Superior robustness and accuracy will be demonstrated together with improved on-product OV performance, promising a process of record metrology solution in specific applications throughout the TD and HVM.
In this paper we present a powerful virtual metrology system to aid in-fab product lot level dispositioning and yield learning. CD and overlay measurement data of different layers are modeled across the wafers and mapped to dense dose, focus, and overlay grids. These are input processing conditions for design-specific computational lithography to predict on full-wafer, full-chip inter-layer overlap area and critical edge-to-edge distances, which are thereafter used to predict electrical failure. The system is composed of an off-line inter-layer hotspot database and an on-line real time dispositioning module. It supports complex multi-patterning stacks with or without self-aligned processes. Example runs have been conducted for 14 nm node metal and via layers, using both FEM-like and typical nominal production wafer data, and the results are as expected from lithographical point of view. Comparing with traditional wafer dispositioning based on static overlay spec and CD spec, our system outputs wafer map stacked with failed dies locations, worst case hotspots contours, root cause analysis, list of worst hotspots and worst dies for inspection, and help litho engineer make an educated decision on wafer dispositioning. This will help fab optimize CD – Overlay process window, improve yield ramp, reduce wafer rework rate, and hence reduce cost, and shorten turn-around-time. The system’s computation is fast and inline real time wafer dispositioning aided by computational lithography is made possible by the system.
Background: To reduce defocus from leveling errors at the wafer edge, modern exposure tools offer a broad range of advanced leveling controls. These additional degrees of freedom offer better leveling performance, but users hesitate to spend the tool time, wafers, and engineering hours necessary to find and maintain the optimal settings experimentally.
Aim: In order to fully explore the potential of advanced leveling controls, an automated, fast simulation method should be introduced.
Approach: Alternative set-point curves and resulting focus residuals are simulated from existing wafer height maps. Optimizations are carried out to obtain the best edge exclusion settings for several dynamic random access memory and NAND flash memory products, across different layers and exposure tools. The simulated focus errors are compared to the POR settings and verified with electrical results.
Results: An efficient optimization algorithm was demonstrated and significant leveling improvements found for a number of use cases. The resulting settings vary substantially between different products, layers, and exposure tools. The impact of the improved leveling performance is verified using electrical data.
Conclusions: The speed of the presented method proves crucial to help lithographers dial in and maintain numerous settings at optimal values across a typical production line.
To reduce defocus from leveling errors at the wafer edge, modern exposure tools offer a broad range of advanced leveling controls. These can be explored fully with minimum experimental effort by simulating alternative set-point curves (z; Rx; Ry) and resulting MA and MSD focus residuals from existing full wafer height maps. In this paper, optimizations are carried out to obtain the best focus edge clearance settings for several DRAM and NAND products, across different layers and exposure tools. The simulated die-fine focus errors are compared to the POR settings and verified with electrical results. Differences across products, layers, and exposure tools are discussed.
In the leading-edge production measuring the geometrical dimensions with e-beam inspection (CD-SEM data) or scatterometry technology (OCD data) is one of the most time-consuming steps without adding value to the wafer. Hence the fabs want to limit the effort to minimize the costs per wafer. On the other hand, the output of the metrology steps is needed to feed the SPC and APC systems with sufficient information. We handle that trade-off with a new sampling scheme optimizer supporting CD-SEM and OCD data.
Generally, we can use the sampling scheme optimization for a set of different features and their measured parameters in parallel. Especially in logic, but also for memory, the focus and dose dependencies of several features may be different. Hence, we optimized the distribution of the measured sites to create a perfect representation of the systematic fingerprint for all important anchor features within one single sampling scheme.
For the verification of the approach we investigated two cases. The first case are dense CD measurements, which are usually needed to create and update intra-field dose corrections. We minimize the number of measured sites significantly and distribute the remaining sites over different fields to ensure a good coverage of the systematic effects. Finally, that allows us a much higher update frequency of the dose corrections and yields in smaller CDU values.
The second case optimized the throughput of an OCD metrology system. The applied high-density sampling scheme for the focus monitoring done on reference wafers takes a lot of time during measuring. That specific type of measurement is done for monitoring and updating the focus reference corrections. With our proposed solution, we can achieve the same quality with respect to the reference measurement with more 50% less measured sites.