Proc. SPIE. 5559, Advanced Signal Processing Algorithms, Architectures, and Implementations XIV
KEYWORDS: Digital signal processing, Radon, Computing systems, Signal processing, Very large scale integration, Transistors, Associative arrays, Computer aided design, Multiplexers, Computer architecture
This paper presents the methods we used to achieve an exhaustive comparison of specific arithmetic operators and the result of this comparative study. The operators we were interested in are modular adders that can be used for Residue Number System (RNS) processors. RNS arithmetic provides an alternative way to produce highly effective multiplication and addition and are, therefore, of great interest for signal processing processors. As modular adders are at the root of any RNS processor, attention must be payed to their design. We expose three different existing designs for such adders and through the construction and use of generators that produce 0.35μ standard cell architectures, we synthesized those three designs for all odd moduli from 4 to 15 bits and measured their performance. Performance was measured after placement and routing of those operators providing precise results. The exhaustive data obtained let us compare those three designs based on size, speed or any combination of those two fore-mentioned factors. Eventually this study gives clues on choosing a specific modular adder for a given modulus and also for choosing the best candidates for a well balanced residue base (i.e. choosing a good set of moduli). Furthermore, it shows that the described parallel modular adder is generally the best choice.