Dr. Pieter Brandt Profile

Dr. Pieter Brandt

at MAPPER Lithography

SPIE Involvement:

Author

Publications (12)

PROCEEDINGS ARTICLE | March 19, 2018

Performance validation of Mapper's FLX-1200

Proc. SPIE. 10584, Novel Patterning Technologies 2018

KEYWORDS: Electron beam lithography, Electron beams, Line width roughness, Optical alignment, Semiconducting wafers, Overlay metrology

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PROCEEDINGS ARTICLE | April 27, 2017

Overlay performance assessment of MAPPER's FLX-1200 (Conference Presentation)

Proc. SPIE. 10144, Emerging Patterning Technologies

KEYWORDS: Wafer-level optics, Lithography, Electron beam lithography, Electron beams, Switching, Lithographic illumination, Photomasks, Integrated optics, Optical alignment, Semiconducting wafers

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Mapper Lithography has introduced its first product, the FLX–1200, which is installed at CEA-Leti in Grenoble (France). This is a mask less lithography system, based on massively parallel electron-beam writing with high-speed optical data transport for switching the electron beams. This FLX platform is initially targeted for 1 wph performance for 28 nm technology nodes, but can also be used for less demanding imaging. The electron source currently integrated is capable of scaling to 10 wph at the same resolution performance, which will be implemented by gradually upgrading the illumination optics. The system has an optical alignment system enabling mix-and-match with optical 193 nm immersion systems using standard NVSM marks. The tool at CEA-Leti is in-line with a Sokudo Duo clean track. Mapper Lithography and CEA-Leti are working in collaboration to develop turnkey solution for specific applications. At previous conferences we have presented imaging results including 28nm node resolution, cross wafer CDu of 2.5nm 3 and a throughput of half a wafer per hour, overhead times included. At this conference we will present results regarding the overlay performance of the FLX-1200. In figure 2 an initial result towards measuring the overlay performance of the FLX-1200 is shown. We have exposed a wafer twice without unloading the wafer in between exposures. In the first exposure half of a dense dot array is exposed. In the second exposure the remainder of the dense dot array is exposed. After development the wafer has been inspected using a CD-SEM at 480 locations distributed over an area of 100mm x 100mm. For each SEM image the shift of the pattern written in the first exposure relative to the pattern written in the second exposure is measured. Cross wafer this shift is 7 nm u+3s in X and 5 nm u+3s in Y. The next step is to evaluate the impact of unloading and loading of the wafer in between exposures. At the conference the latest results will be presented.

PROCEEDINGS ARTICLE | March 22, 2016

Non-CAR resists and advanced materials for Massively Parallel E-Beam Direct Write process integration

Proc. SPIE. 9777, Alternative Lithographic Technologies VIII

KEYWORDS: Lithography, Electron beam lithography, Electron beams, Etching, Silicon, Scanning electron microscopy, Line width roughness, Neodymium, Semiconducting wafers, Surface conduction electron emitter displays

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PROCEEDINGS ARTICLE | March 22, 2016

Complete data preparation flow for Massively Parallel E-Beam lithography on 28nm node full-field design

Proc. SPIE. 9777, Alternative Lithographic Technologies VIII

KEYWORDS: Lithography, Electron beam lithography, Point spread functions, Metrology, Logic, Optical lithography, Data modeling, Calibration, Manufacturing, Electroluminescence, Software development, Optical simulations, Critical dimension metrology, Photoresist processing, Semiconducting wafers, Electronic design automation

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Massively parallel mask-less electron beam lithography (MP-EBL) offers a large intrinsic flexibility at a low cost of ownership in comparison to conventional optical lithography tools. This attractive direct-write technique needs a dedicated data preparation flow to correct both electronic and resist processes. Moreover, Data Prep has to be completed in a short enough time to preserve the flexibility advantage of MP-EBL. While the MP-EBL tools have currently entered an advanced stage of development, this paper will focus on the data preparation side of the work for specifically the MAPPER Lithography FLX-1200 tool [1]-[4], using the ASELTA Nanographics Inscale software. The complete flow as well as the methodology used to achieve a full-field layout data preparation, within an acceptable cycle time, will be presented. Layout used for Data Prep evaluation was one of a 28 nm technology node Metal1 chip with a field size of 26x33mm², compatible with typical stepper/scanner field sizes and wafer stepping plans. Proximity Effect Correction (PEC) was applied to the entire field, which was then exported as a single file to MAPPER Lithography’s machine format, containing fractured shapes and dose assignments. The Soft Edge beam to beam stitching method was employed in the specific overlap regions defined by the machine format as well. In addition to PEC, verification of the correction was included as part of the overall data preparation cycle time. This verification step was executed on the machine file format to ensure pattern fidelity and accuracy as late in the flow as possible. Verification over the full chip, involving billions of evaluation points, is performed both at nominal conditions and at Process Window corners in order to ensure proper exposure and process latitude. The complete MP-EBL data preparation flow was demonstrated for a 28 nm node Metal1 layout in 37 hours. The final verification step shows that the Edge Placement Error (EPE) is kept below 2.25 nm over an exposure dose variation of 8%.

SPIE Journal Paper | August 12, 2015

Comparison between e-beam direct write and immersion lithography for 20-nm node

Sardana, Charu , Ibbotson, Dale , Fay, Aurélien , Brandt, Pieter , Wieland, Marco

JM3 Vol. 14 Issue 03

KEYWORDS: Electron beam direct write lithography, Photovoltaics, Lithium, Immersion lithography, Electron beam lithography, Lithography, Electronic design automation, Field programmable gate arrays, Metals, Optical proximity correction

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SPIE Journal Paper | July 2, 2015

Alternative stitching method for massively parallel e-beam lithography

Brandt, Pieter , Tranquillin, Céline , Wieland, Marco , Bayle, Sébastien , Milléquant, Matthieu , Renault, Guillaume

JM3 Vol. 14 Issue 03

KEYWORDS: Electron beam lithography, Monte Carlo methods, Electroluminescence, Metals, Nano opto mechanical systems, Lithography, Error analysis, Semiconducting wafers, Critical dimension metrology, Overlay metrology

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PROCEEDINGS ARTICLE | March 19, 2015

Ready for multi-beam exposure at 5kV on MAPPER tool: lithographic and process integration performances of advanced resists/stack

Proc. SPIE. 9423, Alternative Lithographic Technologies VII

KEYWORDS: Lithography, Electron beam lithography, Etching, Metals, Silicon, Resistance, Scanning electron microscopy, Extreme ultraviolet, Line width roughness, System on a chip

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PROCEEDINGS ARTICLE | March 19, 2015

Alternative stitching method for massively parallel e-beam lithography

Proc. SPIE. 9423, Alternative Lithographic Technologies VII

KEYWORDS: Lithography, Electron beam lithography, Cadmium, Metals, Electroluminescence, Monte Carlo methods, Immersion lithography, Critical dimension metrology, Semiconducting wafers, Current controlled current source

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PROCEEDINGS ARTICLE | March 19, 2015

Comparison between e-beam direct write and immersion lithography for 20nm node

Proc. SPIE. 9423, Alternative Lithographic Technologies VII

KEYWORDS: Lithography, Photovoltaics, Electron beam lithography, Metals, Field programmable gate arrays, Photomasks, Optical proximity correction, Critical dimension metrology, Electron beam direct write lithography, Electronic design automation

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SPIE Journal Paper | August 11, 2014

Demonstration of electronic design automation flow for massively parallel e-beam lithography

Brandt, Pieter , Belledent, Jérôme , Tranquillin, Céline , Figueiro, Thiago , Meunier, Stéfanie , Bayle, Sébastien , Fay, Aurélien , Milléquant, Matthieu , Icard, Beatrice , Wieland, Marco

JM3 Vol. 13 Issue 03

KEYWORDS: Electron beam lithography, Electronic design automation, Critical dimension metrology, Raster graphics, Point spread functions, Semiconducting wafers, Lithography, Modulation, Optical proximity correction, Data conversion

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For proximity effect correction in 5 keV e-beam lithography, three elementary building blocks exist: dose modulation, geometry (size) modulation, and background dose addition. Combinations of these three methods are quantitatively compared in terms of throughput impact and process window (PW). In addition, overexposure in combination with negative bias results in PW enhancement at the cost of throughput. In proximity effect correction by over exposure (PEC-OE), the entire layout is set to fixed dose and geometry sizes are adjusted. In PEC-dose to size (DTS) both dose and geometry sizes are locally optimized. In PEC-background (BG), a background is added to correct the long-range part of the point spread function. In single e-beam tools (Gaussian or Shaped-beam), throughput heavily depends on the number of shots. In raster scan tools such as MAPPER Lithography’s FLX 1200 (MATRIX platform) this is not the case and instead of pattern density, the maximum local dose on the wafer is limiting throughput. The smallest considered half-pitch is 28 nm, which may be considered the 14-nm node for Metal-1 and the 10-nm node for the Via-1 layer, achieved in a single exposure with e-beam lithography. For typical 28-nm-hp Metal-1 layouts, it was shown that dose latitudes (size of process window) of around 10% are realizable with available PEC methods. For 28-nm-hp Via-1 layouts this is even higher at 14% and up. When the layouts do not reach the highest densities (up to 10∶1 in this study), PEC-BG and PEC-OE provide the capability to trade throughput for dose latitude. At the highest densities, PEC-DTS is required for proximity correction, as this method adjusts both geometry edges and doses and will reduce the dose at the densest areas. For 28-nm-hp lines critical dimension (CD), hole&dot (CD) and line ends (edge placement error), the data path errors are typically 0.9, 1.0 and 0.7 nm (3σ) and below, respectively. There is not a clear data path performance difference between the investigated PEC methods. After the simulations, the methods were successfully validated in exposures on a MAPPER pre-alpha tool. A 28-nm half pitch Metal-1 and Via-1 layouts show good performance in resist that coincide with the simulation result. Exposures of soft-edge stitched layouts show that beam-to-beam position errors up to ±7 nm specified for FLX 1200 show no noticeable impact on CD. The research leading to these results has been performed in the frame of the industrial collaborative consortium IMAGINE.

PROCEEDINGS ARTICLE | March 28, 2014

Demonstration of EDA flow for massively parallel e-beam lithography

Proc. SPIE. 9049, Alternative Lithographic Technologies VI

KEYWORDS: Lithography, Electron beam lithography, Point spread functions, Nano opto mechanical systems, Deconvolution, Raster graphics, Critical dimension metrology, Data conversion, Semiconducting wafers, Electronic design automation

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PROCEEDINGS ARTICLE | March 26, 2013

Matching of beams on the MAPPER MATRIX tool: a simulation study

Proc. SPIE. 8680, Alternative Lithographic Technologies V

KEYWORDS: Lithography, Electron beam lithography, Point spread functions, Electron beams, Error analysis, Line width roughness, Optical simulations, Raster graphics, Critical dimension metrology, Semiconducting wafers

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So far, the CMOS technology roadmap has been consistent with Moore’s law, even if manufacturing photolithography tools are now operating beyond their resolution limit. This has been made feasible at the expense of an intensive joint work between designers and process people who have successfully enabled double patterning processes. Tools that can provide photo lithographers with some relief are on their way although not yet in production. Among them, massively parallel mask-less electron beam lithography stands out as a serious candidate since it can achieve the required resolution at the right cost of ownership provided targeted throughput performance is reached. This paper focuses on this latter technique and more precisely, reports on simulation works performed using an emulator of the high volume manufacturing tool being developed by MAPPER Lithography, called MATRIX. In a nutshell, the MATRIX tool will operate using more than 13,000 beams, each one writing a stripe 2μm wide. Each beam itself will be composed of 49 individual sub-beams that can be blanked independently in order to write pixels onto the wafer. The residual placement errors and any current mismatch between the beams will be measured in-situ and corrected through the data path. In order to validate that this concept can actually work, the authors have built an off-line emulator of the data treatment performed down to the information sent to the blanker. It has then been plugged into an electron beam simulator such that the performance on real designs can be tested. In this paper, the methodology used for the corrections is explained as well as the validation process applied. The results of an extensive statistical study are presented showing CD, placement and residual scaling errors simulated on a set of predefined key structures assuming current and misplacement ranges within the MATRIX tool specifications, applying various correction solutions. Based on the collected data, it is shown that CD uniformity on the MATRIX tool is better than +/-10% 3σ taking into account data path, beam variation, stitching and shot noise effects, meeting specifications for circuits designed at 64nm pitch.

Showing 5 of 12 publications

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