A novel Mesh optical interconnection board configuration in free-space is considered in this paper. Based on Mesh optical interconnection topology principle, this design is specially designed for integrated chip interconnection on high performance occasion as tiny satellites. The system uses VCSELs as electronic-to-optics converter modules to implement conversion between electronic signals and optical ones. Then optical signals, which have better anti-interference than electronic signals, propagate in free-space in a robust way. And at the interconnected chip side, which could only process electronic signals, optical signals are needed to be converted by PIN arrays into electronic ones. All interconnections are skillfully finished by certain cube prisms and inclined 45o reflecting mirrors and limited on the optical-waveguide layer inserted in a PCB board. This paper emphasizes on the configuration of an interconnecting unit (considered as a processing element) and its connecting manner. The design aims at light-weight, small-bulk, great anti-interference, advantages at better robustness, lager throughput, especially suitable for data switch, data propagation and IC interconnection on the tiny satellite.
RRP has two means to transmit data: store-and-forward and cut-through. In this paper, the high and low priority packet transfer delay of the N nodes Resilient Packet Rings (RPR) in store-and-forward architecture is analyzed based on the queuing theory. According to queuing theory, we set up the nodes model and analyzed the factors that influenced the packet transfer delay in a constrained condition. By calculation and simulation, the result indicates that both high priority and low priority packets’ delay increase with the node number N of the RPR rings. The high priority traffic has less packet delay than the low priority traffic at the same node number N. The increase of the low priority transfer delay is much larger than the high priority traffic with the increase of the node number.
This paper reported an improved optical switching network configuration based on optical interconnection technology with vertical cavity surface emitting laser (VCSEL) array. The optical switching network consists of two-level optical interconnection backplane. It can connect 64 nodes with parallel optical links. The first level of optical interconnection backplane includes eight 8×8 crossbar interconnect sub-networks. Instead of one 8×8 crossbar interconnect sub-network in the second level of the optical interconnection backplane adopted in our original configuration, the second level of optical interconnection backplane has two 8×8 Crossbar interconnect sub-networks in this improved configuration. So the blocking rate is decreased. VCSEL-based parallel optoelectronic I/O interface is used as O/E conversion. Every I/O parallel interface between optical interconnection network and every node includes 18 VCSEL emitter pixels, 18 PIN receiver pixels. In order to couple 18 signal light beam array into optical fiber array ribbon, a fabrication technique based on the high precise position slot is used for assembling optical fiber array interface. A configuration of coupling packaging for the VCSEL pixel array to the fiber array with 45° end surface is also presented in this paper. An optical data transmission rate between interconnection nodes is 5Gb/s which is transmitted by the optical fiber ribbon-based parallel optical data links with 2 channels at data rate of 2.5Gb/s per channel. The aggregate bandwidth of 360Gbps for an 8×8 Crossbar optical fiber interconnect network backplane is achieved. The reliability of the fiber array with 45° end surface is tested in our experiment.
A 5 to 10 Gbps bandwidth optical interconnecting and switching network system used on parallel computing is introduced in this paper. This system provides a high bandwidth to meet the request of high bandwidth of the parallel computing. Optics is used to be a media to carry data and optical crossbar interconnection board is used to switch data in this system. It comes over the inherent disadvantage of the R, L, C delay and clock skew of the electronics interconnection. This system has good stability and scalability.