Extreme ultraviolet lithography (EUVL) tool development achieved a big milestone last year as two full-field
Alpha Demo Tools (ADT) were shipped to customers by ASML. In the future horizon, a full field "EUV1" exposure
tool from Nikon will be available by the end of 20071 and the pre-production EUV exposure tools from ASML are
targeted for 20092. It is essential that high quality EUVL masks can be made and delivered to the EUVL tool users to
support the technology development. In the past year, we have demonstrated mask fabrication with low stress absorber
deposition and good etch process control yielding a vertical etch profile and a mask CD control of 5.7 nm for 32 nm (1x)
space and 7.4 nm for 32 nm (1x) lines. Mask pattern resolution of 15 nm (1x) dense lines was achieved. Full field
reflective mask die-to-die inspection at a 125nm pixel size was demonstrated after low defect multilayer blanks became
In this paper, we will present details of the Intel EUVL Mask Pilot Line progress in EUVL mask defect reduction,
pattern CD performance, program defect mask design and inspection, in-house absorber film development and its
performance, and EUVL metrology tool development. We will demonstrate an overall improvement in EUV mask
manufacturing readiness due to our Pilot Line activities.
Alternating Phase Shift Mask (APSM) Technology has been developed and successfully implemented for the poly gate of 65nm node Logic application at Intel. This paper discusses the optimization of the mask design rules and fabrication process in order to enable high volume manufacturability. Intel's APSM technology is based on a dual sided trenched architecture. To meet the stringent OPC requirements associated with patterning of narrow gates required for the 65nm node, Chrome width between the Zero and Pi aperture need to be minimized. Additionally, APSM lithography has an inherently low MEEF that furthermore, drives a narrower Chrome line as compared to the Binary approach. The double sided trenched structure with narrow Chrome lines are mechanically vulnerable and prone to damage when exposed to conventional mask processing steps. Therefore, new processing approaches were developed to minimize the damage to the patterned mask features. For example, cleaning processes were optimized to minimize Chrome & quartz damage while retaining the cleaning effectiveness. In addition, mask design rules were developed which ensured manufacturability. The narrow Chrome regions between the zero and Pi apertures severely restrict the tolerance for the placement of the second level resists edges with respect to the first level. UV Laser Writer based resist patterning capability, capable of providing the required Overlay tolerance, was developed, An AIMS based methodology was used to optimize the undercut and minimize the aerial image CD difference between the Zero and Pi apertures.
Phase shift mask (PSM) applications are becoming essential for addressing the lithography requirements of the 65 nm technology node and beyond. Many mask writer properties must be under control to expose the second level of advanced PSM: second level alignment system accuracy, resolution, pattern fidelity, critical dimension (CD) uniformity and registration. Optical mask writers have the advantage of process simplicity for this application, as they do not require a discharge layer. This paper discusses how the mask writer properties affect the error budget for printing the second level. A deep ultraviolet (DUV) mask writer with a spatial light modulator (SLM) is used in the experimental part of the paper. Partially coherent imaging optics at the 248 nm wavelength provide improved resolution over previous systems, and pattern fidelity is optimized by a real-time corner enhancement function. Lithographic performance is compared to the requirements for second level exposure of advanced PSM. The results indicate sufficient capability and stability for 2nd level alternating PSM patterning at the 65 nm and 45 nm nodes.
Extreme Ultraviolet Lithography (EUVL) reflective mask blank development includes low thermal expansion material fabrication, mask substrate finishing, reflective multi-layer (ML) and capping layer deposition, buffer (optional)/absorber stack deposition, EUV specific metrology, and ML defect inspection. In the past, we have obtained blanks deposited with various layer stacks from several vendors. Some of them are not commercial suppliers. As a result, the blank and patterned mask qualities are difficult to maintain and improve. In this paper we will present the evaluation results of the EUVL mask pattering processes with the complete EUVL mask blanks supplied by the commercial blank supplier. The EUVL mask blanks used in this study consist of either quartz or ULE substrates which is a type of low thermal expansion material (LTEM), 40 pairs of molybdenum/silicon (Mo/Si) ML layer, thin ruthenium (Ru) capping layer, tantalum boron nitride (TaBN) absorber, and chrome (Cr) backside coating. No buffer layer is used. Our study includes the EUVL mask blank characterization, patterned EUVL mask characterization, and the final patterned EUVL mask flatness evaluation.