In this paper, we describe an integrated design space analysis approach consisting of full factorial layout
generation, lithography simulations with added proximity effects, and rigorous statistical analysis through monte-carlo
simulations which is used in the evaluating interconnects. This agile Design rule development process provides a quick
turnaround time to down-select the potential layout configurations that can offer a competitive, robust and reliable
design and manufacturing. Further layout and placement optimization is carried out to evaluate intra-cell, inter-cell and
cell boundary situations, which are critical for a place and routed block. These interconnects developed using the
integrated approach has been the key contributor to give 20-30% higher performance at the same Iddq leakage for 8T
libraries compared to Single Diffusion break or Double Diffusion break based 12T libraries in 22FDX Technology.
To provide insights into best practices of constructing an OPC recipe that suppresses wafer image rippling, we design versatile fragmentation rules with respect to the model-based resist image. Specifically, by recognizing that rippling effect exists before fragmentation, we conduct a coarse simulation with default engine settings and extract raw ripple sinusoidal components associated with signature geometries along all dimensions. The signal is predominantly optical, hence a good representation of the unfiltered diffraction. By referencing the rippling periodic features, we derive a global solution for fragmentation with full respect to geometrical boundary conditions. The methodology enables us to generate a robust fragmentation solution with minimum trial and error and improve target convergence especially along unfavorable dimensions.
Traditional physical design verification tools employ a deck of known design rules, each of which has a pre-defined pass/fail criteria associated with it. While passing a design rule deck is a necessary condition for a VLSI design to be manufacturable, it is not sufficient. Other physical design profiling decks that attempt to obtain statistical information about the various critical dimensions in the VLSI design lack a systematic methodology for rule enumeration. These decks are often inadequate, unable to extract all the interlayer and intralayer dimensions in a design that have a correlation with process yield. The Physical Design Analyzer is a comprehensive design analysis tool built with the objective of exhaustively exploring design-process correlations to increase the wafer yield.
Optical Proximity Correction (OPC) is a compute-intensive process used to generate photolithography mask shapes at advanced VLSI nodes. Previously, we reported a modified two-step OPC flow which consists of a first pattern replacement step followed by a model based OPC correction step . We build on this previous work and show how this hybrid flow not only improves full chip OPC runtime, but also significantly improves mask correction consistency and overall mask quality. This is demonstrated using a design from the 20nm node, which requires the use of model based SRAF followed by model based OPC to obtain the full mask solution.
Pattern based design rule checks have emerged as an alternative to the traditional rule based design rule checks in the VLSI verification flow . Typically, the design-process weak-points, also referred as design hotspots, are classified into patterns of fixed size. The size of the pattern defines the radius of influence for the process. These fixed sized patterns are used to search and detect process weak points in new designs without running computationally expensive process simulations. However, both the complexity of the pattern and different kinds of physical processes affect the radii of influence. Therefore, there is a need to determine the optimal pattern radius (size) for efficient hotspot detection. The methodology described here uses a combination of pattern classification and pattern search techniques to create a directed graph, referred to as the Pattern Association Tree (PAT). The pattern association tree is then filtered based on the relevance, sensitivity and context area of each pattern node. The critical patterns are identified by traversing the tree and ranking the patterns. This method has plausible applications in various areas such as process characterization, physical design verification and physical design optimization. Our initial experiments in the area of physical design verification confirm that a pattern deck with the radius optimized for each pattern is significantly more accurate at predicting design hotspots when compared to a conventional deck of fixed sized patterns.
We treat the OPC engine with a classical dynamics perspective, and quantify its potential to converge in
all dimensions. The inherent engine weakness is thus taken into account for retargeting planning.
Specifically, we follow the one-dimensional helical spring model, and calculate the retarget amount as an
analogy to the spring restoring force, and eventually improve the wafer target convergence. Unlike
conventional measures, this methodology does not require patching or rebuilding the OPC engine,
therefore minimizes the cycle time. Meanwhile, it entails little risk by causing no impact on the mask
solution outside the retargeted region, thereby compartmentalizing the treatment.
Techniques to control Across Chip CD Variation are very important in IC design, since it directly impacts the electrical timing and
functionality of the designs. VLSI designs today include a rich variety of electrical devices (different gate oxide thicknesses, different
threshold voltages, etc.) to provide the much needed flexibility to the chip designer. These devices occur at different proximities and
different densities on a full chip design. In this paper, we describe a method for improving and ensuring design-to-mask (D2M) quality
via a quantitative relationship between design specification and full chip tapeout results. This is done by applying a layout profiling
technique with the aim of capturing comprehensive representation of the design space, this method ensures the quality of design-to-mask
flow prior to release OPC data to mask house.
Full chip model based Optical Proximity Correction (OPC) at
advanced nodes involves iteratively modifying the drawn polygon shapes
while simulating them through complex optical and resist models. Due to
the computational complexity of the models and the large size of VLSI
designs, these mask simulations run for very long times. In this study we
propose a pattern replacement step to generate a partial mask solution
before applying model based OPC correction. Since the pattern replacement
step is very fast and model based OPC has to be applied only to a
portion of the design, total mask generation runtime is significantly reduced.
A methodology is described wherein a calibrated model-based ‘Virtual’ Variable Shaped Beam (VSB) mask writer
process simulator is used to accurately verify complex Optical Proximity Correction (OPC) and Inverse Lithography
Technology (ILT) mask designs prior to Mask Data Preparation (MDP) and mask fabrication. This type of
verification addresses physical effects which occur in mask writing that may impact lithographic printing fidelity
and variability. The work described here is motivated by requirements for extreme accuracy and control of
variations for today’s most demanding IC products. These extreme demands necessitate careful and detailed
analysis of all potential sources of uncompensated error or variation and extreme control of these at each stage of
the integrated OPC/ MDP/ Mask/ silicon lithography flow. The important potential sources of variation we focus on
here originate on the basis of VSB mask writer physics and other errors inherent in the mask writing process. The
deposited electron beam dose distribution may be examined in a manner similar to optical lithography aerial image
analysis and image edge log-slope analysis. This approach enables one to catch, grade, and mitigate problems early
and thus reduce the likelihood for costly long-loop iterations between OPC, MDP, and wafer fabrication flows. It
moreover describes how to detect regions of a layout or mask where hotspots may occur or where the robustness to
intrinsic variations may be improved by modification to the OPC, choice of mask technology, or by judicious design
of VSB shots and dose assignment.