LELE double patterning technology is being deployed for 20nm production. With the use of two separate litho-etch steps in the lithography of one layer, LELE doubles the pitch achievable in the tradional single litho-etch step. However, as wavelength of the light used in each litho-etch step is as before, the need for OPC remains, and is even more crucial.
In this paper, we will present the needs and mechanisms for simultaneous OPC for both masks, the extra freedom avaliable in DP OPC, and the extra consideration needed in developing LELE OPC recipe such as SRAF insertion. biasing.
A typical post-out flow data path at the IC Fabrication has following major components of software
based processing - Boolean operations before the application of resolution enhancement techniques
(RET) and optical proximity correctin (OPC), the RET and OPC step [etch retargeting, sub-resolution
assist feature insertion (SRAF) and OPC], post-OPCRET Boolean operations and sometimes in the
same flow simulation based verification. There are two objectives that an IC Fabrication tapeout flow
manager wants to achieve with the flow - predictable completion time and fastest turn-around time
(TAT). At times they may be competing. There have been studies in the literature modeling the turnaround
time from historical data for runs with the same recipe and later using that to derive the
resource allocation for subsequent runs. . This approach is more feasible in predominantly
simulation dominated tools but for edge operation dominated flow it may not be possible especially if
some processing acceleration methods like pattern matching or hierarchical processing is involved. In
this paper, we suggest an alternative method of providing target turnaround time and managing the
priority of jobs while not doing any upfront resource modeling and resource planning. The methodology
then systematically either meets the turnaround time need and potentially lets the user know if it will
not as soon as possible. This builds on top of the Calibre Cluster Management (CalCM) resource
management work previously published . The paper describes the initial demonstration of the
With 20nm production becoming a reality, research has started to focus on the technology needs for 14nm. The LELE
double patterning used in 20nm production will not be able to resolve M1 for 14nm. Main competing enabling
technologies for the 14nm M1 are SADP, EUV, and LELELE (referred as LE3 thereafter) triple patterning.
SADP has a number of concerns of 1. density, as a layout geometry needs to stay complete as a whole, and can not be
broken; 2. the complexity in SADP mask generation and debug feedback to designers; 3. the subtraction nature
of the trim mask further complicates OPC and yield. While EUV does not share those concerns, it faces significant
challenges on the manufacturing equipment side.
Of the SADP concerns, LE3 only shares that of complexity involved in mask generation and intuitive debug
feedback mechanism. It does not require a layout geometry to stay as a whole, and it benefits from the affinity to
LELE which is being deployed for 20nm production. From a process point of view, this benefit from affinity to LELE
is tremendous due to the data and knowledge that have been collected and will be coming from the LELE deployment.
In this paper, we first recount the computational complexity of the 3-colorability problem which is an integral
part of a LE3 solution. We then describe graph characteristics that can be exploited such that 3-colorability
is equivalent under divide-and-conquer. Also outlined are heuristics, which are generally applied in solving
computationally intractable problems, for the 3-colorability problem, and the importance in choosing appropriate
worst-case exponential runtime algorithms. This paper concludes with a discussion on the new hierarchical problem
that faces 3-colorability but not 2-colorability and proposals for non-3-colorability feedback mechanism.
Litho-etch-litho-etch (LELE) is the double patterning (DP) technology of choice for 20 nm contact, via, and lower metal
layers. We discuss the unique design and process characteristics of LELE DP, the challenges they present, and various
○ We examine DP design methodologies, current DP conflict feedback mechanisms, and how they can help
designers identify and resolve conflicts.
○ In place and route (P&R), the placement engine must now be aware of the assumptions made during IP cell
design, and use placement directives provide by the library designer. We examine the new effects DP
introduces in detail routing, discuss how multiple choices of LELE and the cut allowances can lead to different
solutions, and describe new capabilities required by detail routers and P&R engines.
○ We discuss why LELE DP cuts and overlaps are critical to optical process correction (OPC), and how a hybrid
mechanism of rule and model-based overlap generation can provide a fast and effective solution.
○ With two litho-etch steps, mask misalignment and image rounding are now verification considerations. We
present enhancements to the OPCVerify engine that check for pinching and bridging in the presence of DP
overlay errors and acute angles.
LELE/LFLE based double patterning (DPT) with ArF water-based immersion systems has emerged as a strong
candidate to first extend lithography to 32nm and below. Mask planning for DPT consists of conflict visualization
when design is not manufacturable with DPT and mask assignment either when it is or despite it is not.
Concurrent with the advancements in double patterning process, there has been active research    
addressing the problem of mask planning. As geometries across the chip can potentially involve in the same
conflict, DPT decomposition has been recognized as unbounded  . We will show in this paper that the
unbounded nature of a potential conflict drawing in geometries from across the chip, however, poses little obstacle
to efficient conflict visualization or mask assignment. Hierarchy already present in design offers different levels
of abstraction for conflicts spanning across various levels of the hierarchy. And pseudo hierarchy from tiles of
fully flattened design are even more amenable in that they are already positioned with respect to the flat view,
and tiles overlap only marginally when they do.
While there have been ample research literature in the mask assignment problem with respect to geometries
within cell or flat view of a design, not much have been published on how hierarchy is addressed or any special
handling needed for peculiar complexities arising from the presence of hierarchy  . Hierarchy adds a subtle
but significant dimension to the mask planning problems. This paper investigates contact layer mask planning
for DPT, and presents results on two new problems due to hierarchical processing.
With each new process technology node, chip designs increase in complexity and size, leading to a steady
increase in data volumes. As a result, mask data prep flows require more computing resources to maintain
the desired turn-around time (TAT) at a low cost. The effect is aggravated by the fact that a mask house
operates a variety of equipment for mask writing, inspection and metrology - all of which, until now,
require specific data formatting. An industry initiative sponsored by SEMI® has established new public
formats - OASIS® (P39) for general layouts and OASIS.MASK (P44) for mask manufacturing equipment -
that allow for the smallest possible representation of data for various applications. This paper will review a
mask data preparation process for mask inspection based on the OASIS formats that also reads
OASIS.MASK files directly in real time into the inspection tool. An implementation based on standard
parallelized computer hardware will be described and characterized as demonstrating throughputs required
for the 45nm and 32nm technology nodes. An inspection test case will also be reviewed.
The data volume is increasing exponentially in mask data preparation (MDP) flows for sub-45nm technologies, but
time to market drives the acceptable total turnaround time. As a reasonable response, more computing resources are
purchased to address these two issues. How to effectively use these resources including the latest CPUs, high-speed
networking, and the fastest data storage devices is becoming an urgent problem to solve. A detailed study is conducted in
an attempt to find an optimal solution to this problem. In particular, how CPU speed, bandwidth of network connections,
and I/O speed of data storage devices affect the total turnaround time (TAT) in a mask data preparation flow is
researched. For a given High Performance Computing (HPC) budget and MDP flow TAT constraints, methodologies to
optimize HPC resources are proposed.
As we delve deeper into subwavelength design and manufacturing challenges and solutions, technologies such as Optical Proximity Correction (OPC) and Phase Shifting Masks (PSM) have become essential to reliabily produce advanced integrated circuits. Alternating PSM (altPSM) has demonstrated many recent successses as an effective means to this end. This paper lays the groundwork for defining the IC design components needed to meet altPSM-compliance requirements. The paper addresses the open question regarding whether we can take into account all the manufacturing requirements and come up with highly abstract manufacturing rules that can be applied to all IC design domains. The paper further proposes a solution with specific rules and algorithms needed to apply altPSM to transistor gate regions, and targeted to various domains of IC design such as verification or place and route. Examples include constraints for routers and placement tools, as well as sign-off rules that can be used by designers as well as by production engineres to fine-tune the process and yield for a given design structure. The usability of such a solution is then analyzed to take the practical aspects of IC design into consideration.