The high bandwidth density and low power consumption characteristics of silicon photonics devices can provide
a high performance interconnect solution for multiprocessor systems. At the same time this technology also
poses a new set of constraints and challenges in architecting, designing, and integrating such systems.
The "macrochip" multiprocessor architecture leverages a photonically interconnected array of processor and/or
memory chips to provide a flexible platform to build heterogeneous systems. The design considerations for such
a system are influenced largely by the system architecture, the programming model and devices needed for
their implementation. This talk will first describe the macrochip platform, technology constraints and potential
interconnect solutions with the various device building blocks. Then it will present some topology choices that
range from a WDM point-to-point interconnect to more complex switched data channel networks. It will close
with a detailed analysis of these design choices and show the impact of the device constraints on performance
and power consumption along with some recent ultra-low power device implementation results.
In this paper we present a computing system that uniquely leverages the bandwidth, density, and
latency advantages of silicon photonic interconnects to enable highly compact supercomputerscale
systems. We present the details of an optically enabled "macrochip" which is a set of
contiguous, optically-interconnected chips that deploy wavelength-division multiplexed (WDM)
enabled by silicon photonics. We describe the system architecture and the WDM point-to-point
network implementation of a "macrochip" providing bisection bandwidth of 10 TBps and discuss
system and device level challenges, constraints, and the critical technologies needed to implement
this system. We present a roadmap to lowering the energy-per-bit of a silicon photonic
interconnect and highlight recent advances in silicon photonics under the UNIC program that
facilitate implementation of a "macrochip" system made of arrayed chips.
We review the progress and challenges in scaling computing systems; discuss the
potential benefits and challenges for achieving optical-interconnects to the chip via the
native integration of silicon photonics components with VLSI electronics; and introduce
the "macrochip" - a collection of contiguous silicon chips enabled by optical proximity
We introduce a novel approach to interconnect multiple chips together with a silicon
photonic WDM point-to-point network enabled by optical proximity communications to act as a
single large piece of logical silicon much larger than a single reticle limit. We call this structure a
macrochip. This non-blocking network provides all-to-all low-latency connectivity while
maximizing bisection bandwidth, making it ideal for multi-core and multi-processor
interconnections. We envision bisection bandwidth up to TBps for an 8x8 macrochip design. And a
5-6x improvement in latency can be achieved when compared to a purely electronic implementation.
We also observe better overall performance over other optical network architectures.