Chip performance and yield are increasingly limited by systematic and random variations introduced during wafer
processing. Systematic variations are layout-dependent and can be broadly classified as optical or non-optical in nature.
Optical effects have their origin in the lithography process including mask, RET, and resist. Non-optical effects are
layout-dependent systematic variations which originate from processes other than lithography. Some examples of nonoptical
effects are stress variations, well-proximity effect, spacer thickness variations and rapid thermal anneal (RTA)
variations. Semiconductor scaling has led to an increase in the complexity and impact of such effects on circuit
parameters. A novel technique for dataprep called electrically-driven optical proximity correction (ED-OPC) has been
previously proposed which replaces the conventional OPC objective of minimization of edge placement error (EPE) with
an electrical error related cost function. The introduction of electrical objectives into the OPC flow opens up the
possibility of compensating for electrical variations which do not necessarily originate from the lithographic process. In
this paper, we propose to utilize ED-OPC to compensate for optical as well as non-optical effects in order to mitigate
circuit-limited variability and yield. We describe the impact of non-optical effects on circuit parameters such as
threshold voltage and mobility. Given accurate models to predict variability of circuit parameters, we show how EDOPC
can be leveraged to compensate circuit performance for matching designer intent. Compared to existing
compensation techniques such as gate length biasing and metal fills, the primary advantage of using ED-OPC is that the
process of fragmentation in OPC allows greater flexibility in tuning transistor properties. The benefits of using ED-OPC
to compensate for non-optical effects can be observed in reduced guard-banding, leading to less conservative designs. In
addition, results show a 4% average reduction in spread in timing in compensating for intra-die threshold voltage
variability, which potentially translates to mitigation of circuit-limited yield.
Yield loss due to process variations can be classified as catastrophic or parametric. Parametric variations can further
be random or systematic in nature. Systematic parametric variations are being projected as a major yield limiter in sub-
65nm technologies. Though several models exist to describe process-induced parametric effects in layouts, there is no
existing design methodology to study the variational (across process window) impact of all these effects simultaneously.
In this paper, we present a methodology for analyzing multiple process-induced systematic and statistical layout
dependent effects on circuit performance. We describe physical design models used to describe four major sources of
parametric variability - lithography, stress, etch and contact resistance - and their impact on device properties. We then
develop a methodology to determine variability in circuit performance based on integrating the above device models
with a circuit simulator like SPICE. A circuit simulation engine for 45nm SOI devices is implemented, which shows the
extent of the impact of layout-dependent systematic variations on circuit parameters like delay and power. Based on the
analysis, we demonstrate that all systematic effects need to be simultaneously included to match the hardware data. We
believe a flow that is capable of understanding process-induced parametric variability will have major advantages in
terms of improving physical design and yield in addition to reducing design to hardware miscorrelations and
advantages in terms of diagnosis and silicon debug.
Existing optical proximity correction tools aim at minimizing edge placement errors (EPE) due to the optical and resist
process by moving mask edges. However, in low-k1 lithography, especially at 45nm and beyond, printing perfect
polygons is practically impossible to achieve in addition to incurring prohibitively high mask complexity and cost. Given
the impossibility of perfect printing, we argue that aiming to reduce the error of electrical discrepancy between the ideal
and the printed contours is a more reasonable strategy. In fact, we show that contours with non-minimal EPE may result
in closer match to the desired electrical performance.
Towards achieving this objective, we developed a new electrically driven OPC (ED-OPC) algorithm. The tool combines
lithography simulation with an accurate contour-based model of shape electrical behavior to predict the on/off current
through a transistor gate. The algorithm then guides edge movements to minimize the error in current, rather than in
edge placement, between current values for printed and target shapes. The results on industrial 45nm SOI layouts using
high-NA immersion lithography models show up to a 5% improvement in accuracy of timing over conventional OPC,
while at the same time showing up to 50% reduction in mask complexity for gate regions. The results confirm that better
timing accuracy can be achieved despite larger edge placement error.