Recent advances in the integrated electronic circuit industry have spurred efforts to develop technologies that efficiently integrate optics and electronics on a single Complementary Metal Oxide Semiconductor (CMOS) chip. Such CMOS technologies can significantly increase circuit functionality and performance at low fabrication and system cost, thereby accelerating the trend of significant growth in this area. The new functionality could include optical based sensors, image processing, and intelligent optical read heads for faster and more efficient data sorting and searching. The reliability of such monolithic CMOS based functions would be drastically improved relative to their bulk optic counterparts. In the optical telecommunications industry, short haul fiber links would benefit from low cost, silicon CMOS based photoreceivers. One of the primary challenges facing the designers in implementing CMOS based optoelectronic circuits is opto-electrical conversion efficiency. The poor optical responsivity of silicon leads to a bottleneck in the optical to electrical conversion for CMOS based photodetectors. This can be compensated in part through more efficient receiver electronics. Efforts have been made to provide mixed signal circuit design to analyze CMOS based high performance, low noise, integrated receiver circuits. This paper evaluates the performance analysis of five types of photoreceiver configurations that were designed for specific applications.
A new multi-technology FPGA (MT-FPGA) architecture has recently been proposed. This new class of programmable hardware allows for the incorporation of a variety of multi-technology blocks like the optical sensor block as described in this paper. Using MT-FPGA technology, a system designer can readily implement any prototype multi-technology system with (1) logic parts in programmable section of MT-FPGA and (2) Multi-technology components by incorporating different multi-technology blocks from standard library. Thus, our new class of multi-technology FPGA will extend the benefits of rapid prototyping, re-configurability and evolvable hardware to multi-technology environments/applications that currently do not benefit from the advantages of programmable hardware. This paper highlights the use of an MT-FPGA chip through the implementation and evaluation of an optical power meter block. This mixed technology block is designed for implementation using a 0.35 micron CMOS process and consists of a p-diffusion to n-well photodetector followed by a wide-swing variable gain differential amplifier and a 4 bit FLASH ADC. The amplifier gain characteristics are adjustable by two analog control signals. One adjusts the gain and the other controls the biasing conditions of the differential amplifier. The last stage of the system is a 4 bit ADC that has a worst case resolution of 0.5 mV.