This paper presents a 10Gb/s partial response (PR) equalizer in 0.18μm CMOS technology. By incorporating a reshaping filter with high-frequency emphasis and the intrinsic roll-off bandwidth of the channel, a duobinary signal is available at the receiver, reducing the bandwidth requirement of high speed communication. To enhance the performance of the PR equalizer, a two-path oversampling technique is used to cope with the time delay variations due to different process corners. Additionally, adjustable capacitance and load calibration technique are also applied to eliminate the process variations further. The chip area including I/O pads occupies 0.835×0.715mm<sup>2</sup> and the power consumption is about 224mW under 1.8V power supply. Post simulation results show that the proposed equalizer works properly at 10Gb/s and more than 70% eye opening can be obtained.
In this paper, a practical 40Gb/s 12:16 converter is implemented for VSR parallel optical transmission.
The converter realizes the functions of mapping OC-768 frame to/from parallel optics. Using two chips
of Altera FPGA and Agilent81250, a complete simplex communication experiment system is built.
Detailed design such as frame synchronization, deskew algorithm and converter are presented. In
addition, we design a SFI-5 interface verifying board to verify the deskew function. Testing results are
also given illustrating that the converter works well.