An improved sense amplifier with speed-up pre-charge scheme is introduced in this paper. What’s more, in order to avoid unexpected fatal damage while reading operation, clamp voltage is adopted. Distinguished with the conventional current sense amplifier, the proposed sense amplifier shortens not only the read access time by reducing the charging time due to parasite capacitor of storage cells but also the delay time because of the RC delay on wire by using two branches of pre-charge circuit at the both ends of bit lines. The simulation result taken in SMIC 28nm process shows that, with 1Kb PCM array, the proposed sense amplifier can efficiently reduce the access time from 33.7ns to 16.5ns.
A novel standby mode scheme with light load efficiency improvement is proposed in this paper, which is especially suitable for modern boost dc-dc converters powered by Li-ion battery. The proposed output load estimator is able to accurately reflect the output load current under light load condition once inductor current enters in the discontinuous conduction mode (DCM). Our experimental results show that the proposed boost dc-dc converter can automatically select approximate PWM switching frequency according to the detected information of the proposed output load estimator, regardless of power supply and inductor value.
This paper presents a 2X/1.5X switched-capacitor charge pump for phase change memory (PCM). For a 16-bitparallelism PCM, the set/reset time is more than 100 ns, and the charge pump should output a minimum 60 mA load current. The proposed charge pump can supply 4.1 V voltage and 0-60 mA current for PCM, with an input voltage range of 2.2-3.5 V. It can also automatically change the power conversion ratio between the 2X/1.5X modes according to input voltage. For the improvement of efficiency and load transient response, an auto-adjustable output regulation scheme is employed. In this scheme, two new reference voltages are introduced and compared with output voltage. Average lasting time of the enable signal changes under different load conditions. The Enable signal then controls booster’s power transistors switching to regulate output voltage. In this way, output voltage was controlled within a permissible range. The charge pump has been designed and simulated in a 40nm CMOS process. The results show maximum power efficiency in 30 mA load current is 90.73%, and conversion ratio control increases the efficiency by 23.06% in 3 V.
This paper presents a fully digital-control soft start mechanism with coefficients Ki optimization for DC-DC power converters. During the soft start phase, a ladder reference voltage steps up gradually to make inductor current ramp up smoothly and overshoot voltage is minimized with the proposed coefficients Ki distribution. Simulation results show that massive inductor current can be well avoided during the soft start process with the proposed soft start mechanism, which only occupies a chip area of 300um×120um.
The widely used traditional Flash memory suffers from its performance limits such as its serious crosstalk problems, and increasing complexity of floating gate scaling. Phase change random access memory (PCRAM) becomes one of the most potential nonvolatile memories among the new memory techniques. In this paper, a 1M-bit PCRAM chip is designed based on the SMIC 40nm CMOS technology. Focusing on the read and write performance, two new circuits with high-speed read operation and highly reliable reset operation are proposed. The high-speed read circuit effectively reduces the reading time from 74ns to 40ns. The double-mode reset circuit improves the chip yield. This 1M-bit PCRAM chip has been simulated on cadence. After layout design is completed, the chip will be taped out for post-test.
Circuit design of an adaptable pulse current source chip is presented in this paper. The pulse current source is supposed to be used to supply Reset and Set current in the phase change memory chip testing system. The value and width of the pulse current source are variable, with the maximum value of 10mA and minimum width of 50ns. Two pulse currents output simultaneously with the same width but different values. A voltage pulse input is used to control the width of pulse current output. This high frequency voltage pulse could induce noise jamming to the inner circuits. To avoid this, a novel ESD and bonding structure is proposed.
An 8Mb phase change random access memory (PCRAM) has been developed by a 130nm 4-ML standard CMOS technology based on the Resistor-on-Via-stacked-Plug (RVP) storage cell structure. This phase change resistor is formed after CMOS logic fabrication. PCRAM can be embedded without changing any logic device and process. The memory cell selector is implemented by a standard 1.2V NMOS device. Aimed at the resistance distributions, lowering the operation current and improving the bit yield, some methods are used to optimize the design of the chip.
A serial peripheral interface (SPI) 16-Kbit phase change memory chip based on 0.13μm CMOS process is designed. It contains a parallel error correcting code (ECC) circuit, which can correct 2 bits in every 8 bits without clock delay, enabling the write and read operations performed at bus speed. All the data transfers in 8-bit groups and can be read or written with write protection scheme by unlimited cycle, in which address can automatically increase one by one. Simulation results show that the chip can work correctly in SPI mode and with ECC scheme. It is now under testing.
A write driver for PCM is designed to improve reliability and bit yield in the write operation, due to the distributions during the phase change process. And the PCM cell can be injected by current or voltage respectively. Meanwhile, owing to the possible variations of the SET process parameters, the designed circuit can generate either multiple stepdown current pulse or multiple step-down voltage pulse. The circuit is developed based on SMIC 130 nm CMOS standard technology. Compared to the traditional constant current pulse programming, the test results show that the proposed multiple step-down current generator for SET operation can improve the uniformity of resistance and bit yield.