Detecting and resolving the true on-wafer-hotspot (defect) is critical to improve wafers’ yield in high volume manufacturing semiconductor foundries. Traditionally, Optical Rule Check (ORC) with computation lithography has been one of the most important techniques to flag potential failure patterns (weak points) after Optical Proximity Correction (OPC), where ORC results are fed back to the OPC team to fix the OPC solution if needed, or fed forward to Contamination Free Manufacturing (CFM) team to improve the inspection accuracy. However, as the integrated circuits process becomes more and more complex with the technology scaling, ORC alone could no longer identify the outlier-alike defects, even though it has helped in resolving most of defects on wafer. Failing to detect yield-killer defects could be due to the lack of sufficient understanding and modeling in terms of etching, CMP, as well as other inter-layer process variations. It has been a struggle for Fab to identify reasonable amount of defects scattered on wafer in order to understand defect mechanisms quickly, thus find ways to fix them in a timely manner. In this paper, we present a fast and accurate Defect Detection and Repair Flow (DDRF) with machine learning (ML) methodology to address the above issues. There are four parts in the DDRF: the first part is on the feature generation and data collection, the second on the ML model building, the third on the full-chip prediction, and the fourth on the hot-spot repair. We use limited amount of known defects found on wafer as input to train the ML model, and then apply the ML model to the full chip for prediction. The wafer verification data showed that our flow achieved more than 80% of defect hit rate with engineered feature extractions and ML model for a 7nm mask. Finally, we analyze the failing mechanism with more available defects, and are able to provide guidance to the OPC development to fix the defects by using the ML model.
As semiconductor manufacturing continues its march towards more advanced technology nodes, it becomes increasingly important to identify and characterize design weak points, which is typically done using a combination of inline inspection data and the physical layout (or design). However, the employed methodologies have been somewhat imprecise, relying greatly on statistical techniques to signal excursions. For example, defect location error that is inherent to inspection tools prevents them from reporting the true locations of defects. Therefore, common operations such as background-based binning that are designed to identify frequently failing patterns cannot reliably identify <i>specific</i> weak patterns. They can only identify an approximate <i>set </i>of possible weak patterns, but within these sets there are many perfectly good patterns. Additionally, characterizing the failure rate of a known weak pattern based on inline inspection data also has a lot of fuzziness due to coordinate uncertainty. SEM (Scanning Electron Microscope) Review attempts to come to the rescue by capturing high resolution images of the regions surrounding the reported defect locations, but SEM images are reviewed by human operators and the weak patterns revealed in those images must be manually identified and classified. Compounding the problem is the fact that a single Review SEM image may contain<i> multiple </i>defective patterns and several of those patterns might not <i>appear</i> defective to the human eye.<p> </p>In this paper we describe a significantly improved methodology that brings advanced computer image processing and design-overlay techniques to better address the challenges posed by today’s leading technology nodes. Specifically, new software techniques allow the computer to analyze Review SEM images in detail, to overlay those images with reference design to detect <i>every</i> defect that might be present in all <i>regions of interest</i> within the overlaid reference design (including several classes of defects that human operators will typically miss), to obtain the exact defect location on design, to compare all defective patterns thus detected against a library of known patterns, and to classify all defective patterns as either <i>new</i> or <i>known</i>. By applying the computer to these tasks, we automate the entire process from defective pattern identification to pattern classification with <i>high precision</i>, and we perform this operation en masse during R & D, ramp, and volume production.<p> </p>By adopting the methodology, whenever a <i>specific</i> weak pattern is identified, we are able to run a series of characterization operations to ultimately arrive at the root cause. These characterization operations can include (a) searching all pre-existing Review SEM images for the presence of the specific weak pattern to determine whether there is any <i>spatial</i> (within die or within wafer) or <i>temporal</i> (within any particular date range, before or after a mask revision, etc.) correlation and (b) understanding the failure rate of the <i>specific</i> weak pattern to prioritize the urgency of the problem, (c) comparing the weak pattern against an OPC (Optical Procimity Correction) Verification report or a PWQ (Process Window Qualification)/FEM (Focus Exposure Matrix) result to assess the likelihood of it being a litho-sensitive pattern, etc. After resolving the specific weak pattern, we will categorize it as known pattern, and the engineer will move forward with discovering new weak patterns.
As the semiconductor process technology moves into more advanced nodes, design and process induced systematic defects become increasingly significant yield limiters. Therefore, early detection of these defects is crucial. Focus Exposure Matrix (FEM) and Process Window Qualification (PWQ) are routine methods for discovering systematic patterning defects and establishing the lithography process window. These methods require the stepper to expose a reticle onto the wafer at various focus and exposure settings (also known as modulations). The wafer is subsequently inspected by a bright field, broadband plasma or an E-Beam Inspection tool using a high sensitivity inspection recipe (i.e. hot scan) that often reports a million or more defects. Analyzing this vast stream of data to identify the weak patterns and arrive at the optimal focus/exposure settings requires a significant amount of data reduction through aggressive sampling and nuisance filtering schemes. However, these schemes increase alpha risk, i.e. the probability of not catching some systematic or otherwise important defects within a modulation and thus reporting that modulation as a good condition for production wafers. In order to reduce this risk and establish a more accurate process window, we describe a technique that introduces image-and-design integration methodologies into the inspection data analysis workflow. <p> </p>These image-and-design integration methodologies include contour extraction and alignment to design, contour-to-design defect detection, defective/nuisance pattern retrieval, confirmed defective/nuisance pattern overlay with inspection data, and modulation-related weak-pattern ranking. The technique we present provides greater automation, from defect detection to defective pattern retrieval to decision-making steps, that allows for statistically summarized results and increased coverage of the wafer to be achieved without an adverse impact on cycle time. Statistically summarized results, lead to objective assessments of the output; and increased coverage, in turn, leads to a more comprehensive assessment of the impact of each pattern defect and each focus/exposure modulation. Overall, this leads to a more accurate determination of the process window.