In this paper, we present the flow and results of contour-based process characterization, modeling and control used for semiconductor manufacturing. First, high-quality contours are extracted from large field of view (FOV) SEM images based on the improved Canny edge detection algorithm. Prior to the contour analysis steps, SEM image distortion correction is performed by using the loworder linear model. When there are repeating cells within one FOV, the N-sigma roughness band of the unit cell is calculated to show the stochastic process variation fingerprint. For SEM images collected from a focus-exposure matrix wafer, the contour-based process window analysis is performed to generate the depth-of-focus map for the full image, enabling precise detection of process window limiting locations. Finally, 3D compact resist models are calibrated by using both inner and outer contours from the same SEM images, which proves to be effective for the prediction of resist top loss related hotspots.
Standard cells are the most critical and reusable elements to build up the whole chip, therefore foundry has to fully qualify the standard cell libraries to ensure their high quality when releasing to the customers for the chip design. To prevent pattern dependent lithographic difficulty in manufacturing is one target of standard cell qualification and becomes mandatory especially in advanced nodes due to tighter design rules and smaller design size. To identify a lithographic problematic standard cell, we have to take its surroundings within the optical diameter range into consideration because lithographic effects are intrinsically context-dependent. One critical step is to imitate standard cells placements in real designs and consider some important factors like VIA location as it impacts the mask shape directly. When the placement is completed, lithographic simulation is performed by LFD (Litho Friendly Design) to highlight risky locations. Every standard cell has to occur enough number of times to make sure the statistics of possibility of being a problem is reliable. The final statistics will instruct engineers on how to handle the problematic standard cells, either standard cell layouts have to be optimized or building a pattern database to prevent the abutments of particular standard cell combinations.
Design technology co-optimization (DTCO) is one of the most critical considerations for yield breakthrough and product ramp-up during the life cycle of a new technology node. Traditional sign-off flow of physical verification cannot guarantee manufacturability totally. Comprehensive design for manufacturing (DFM) check should be involved in flow of product tape-out in order to recognize the patterning and other process challenges which would limit the wafer yield. The process related hotspots were pre-defined with the aid of process related simulation kits on cell, block as well as full chip levels. A systematic DTCO methodology including fabless process friendly flow with lithography friendly design (LFD), pattern match and chemical mechanical planarization (CMP) check, resolution enhancement technology (RET) synthesis, process window check for sensitive patterns as well as weak pattern library assisted circuit diagnosis was as an example of DTCO application at 14/12nm in this paper.
It’s desirable to gain high yield and good performance for memory products. Designers have to do some advanced DFM checking on their designs and fix all the critical design issues to be correct by construction before manufacturing. One of the DFM checking items is the litho hotspot checking, LFD (Litho Friendly Design) is the tool adopted for that checking due to its user friendly interface for designers and being able to be integrated with other tools for the advanced checking flow development. One challenge to enable this checking as the signoff item is the long runtime due to the computing-intensive litho simulation. Multiple ways have been figured out to reduce the runtime, for instance, hierarchical checking flow similar to hierarchical design flow under the assumption that many design blocks are reused on the top level; simulation only on the area selected by weak pattern candidates stored in a pattern matching library; simulation only on the unique pattern area by firstly decomposing the layout. All these approaches always tradeoff between runtime and simulation accuracy and come to use with different expectations as the process gradually matures. This paper introduces another technique to reduce the simulation time. This technique is essentially a pattern matching extended application and will be introduced in detail in the paper.
Silicon weak pattern exploration becomes more and more attractive for yield improvement and design robustness as these proven silicon weak patterns or hotspots directly reveals process weakness and should be avoided to occur on the chip design. At the very beginning, only a few known hotspot patterns are available as seeds to initialize the weak pattern accumulation process. Machine learning technique can be utilized to expand the weak pattern database, the data volume is critical for machine learning. Fuzzy patterns are built and more potential hotspots locations are found and sent to YE team to confirm, thus more silicon proven data is available for machine learning model training, both good patterns and bad patterns are valuable for the training data set. The trained machine learning model is then used for new hotspots prediction. The outcome from the machine learning prediction need to be validated by silicon data in the first few iterations. When a reliable machine learning model is ready for hotspots detection, designers can run hotspot prediction at the design stage. There are some techniques in training the mode and will be discussed in details in the paper.
Via location and metal coverage have direct correlation. Optical proximity correction (OPC) always do selective sizing for metal to offer enough via enclosure, such as extending line end or doing external expansion for related metal edge. Hence via poor landing or metal bridging are both potential hotspots. For 14nm technology node and below, process related weak patterns are highly correlated with via locations and corresponding metal dimensions. A via optimization methodology has been put forward to enhance the robustness of design for physical design in fabless. With the aid of lithography check, the yield killers with high potential relativity with vias will be conducted root cause analysis. This paper describes the main solutions for fabless, including pin location blockage, via shift, via shape change, metal sizing change and so on within design rule check (DRC) constraints. The simulation experiment results prove the effective of these solutions due to related simulated yield killers being eliminated.
Chemical-mechanical polishing (CMP) is a key process in integrated circuit (IC) manufacturing. Successful fabrication of semiconductor devices is highly dependent on the final planarity of the processed layers. Post-CMP topography variation may cause degradation of the circuit performance. Moreover, the depth-of-focus (DOF) requirement is critical for lithography of subsequent layers. As such, planarity requirements are critical for maintaining IC manufacturing technology scaling trends, and supporting device innovation. To mitigate post-CMP planarity issues, dummy fill insertion has become a commonly-used technique. Many factors impact dummy fill insertion results, including fill shapes, sizes, and the spacing between both fill shapes and the drawn layout patterns. The goal of the CMP engineer is to optimize design planarity, but the variety of fill options means just verifying the design rules for fill is a challenging task. This data collection currently requires a long development cycle, consuming a great deal of time and resources. In this paper, we show how CMP modeling can help resolve these issues by applying CMP modeling and simulations to drive Calibre YieldEnhancer SmartFill parameters that have been optimized for dummy fill. Additional capabilities in the SmartFill functionality automate CMP hotspot fixing steps. Using CMP simulations, engineers can get feedback about post-CMP planarity for given fill options in a much shorter time. Not only does this move dummy fill optimization experiments from a real lab into a virtual lab of CMP modeling and simulation, but it also provides more time for these experiments, providing improved results.
High yield is always demanded in IC manufacturing, however, as process variations and random particles are part of the manufacturing process in nature, yield and circuit performance are inevitably impacted by these factors especially in advanced nodes. Even so, there’s often some room to polish designs to be manufacturing friendly. The design for manufacturability (DFM) approach has been taken to optimize designs to minimize process variation impact on the yield and performance. One area gaining success toward yield improvement is VIA (Vertical Interconnect Access) design optimization. There are some technical approaches that designers may take: adding redundant VIA at possible spots without increasing the design area is a proven way to address random particle induced VIA void issues; increasing VIA enclosure area by shifting VIA to an optimum location effectively minimizes masks misalignment induced enclosure issues, and note that shifting VIA needs to consider some complex situations when clustered VIAs constrain each other. There are also other circumstances that need to be considered and handled depending on specific manufacturing process. All these contents will be presented in detail in the paper.
Proc. SPIE. 10962, Design-Process-Technology Co-optimization for Manufacturability XIII
KEYWORDS: Data modeling, Copper, Manufacturing, Chemical vapor deposition, 3D modeling, Semiconducting wafers, Process modeling, Chemical mechanical planarization, Back end of line, Design for manufacturability
Vertical NAND (3D NAND) designs provide unprecedented improvements in input/output (I/O) performance and storage density, but require additional analysis to ensure manufacturing and market success. While 3D stacked architectures greatly reduce chip area at advanced technology nodes, greater topology uniformity is essential, not only for inter-layers stacking, but also for the chip bonding process. As the link between design and manufacturing, design for manufacturing (DFM) predicts potential manufacturing issues during the design stage, enabling design teams to modify the layout and mitigate the risk. The copper interconnect process can be modeled through multiple process steps, from film stacking, etch, and copper deposition to polishing. The simulated topology of a given design predicts potential risky areas that may be fixed by changing designs or inserting dummy fill prior to manufacturing. This simulation is a useful technique during yield ramp-up, and can shorten the cycle from design to manufacturing. This paper presents a solution for BEOL CMP modeling and analysis on BEOL copper interconnect of a 3D NAND flow.
Chemical-mechanical polishing (CMP) is a key process that reduces chip topography variation during manufacturing. Any variation outside of specifications can cause hotspots, which negatively impact yield. As technology moves forward, especially in memory processes like 3D NAND, high-quality surface planarity is required to overcome manufacturing challenges in each process step. Any topography variation in the front-end-of-line (FEOL) must be taken into consideration, as it may dramatically impact the surface planarity achieved by subsequent manufacturing steps. Rule-based checking of the design is not sufficient to discover all potential CMP hotspots. An accurate FEOL CMP model is necessary to predict design-induced CMP hotspots and optimize the use of dummy fill to alleviate manufacturing challenges. While back-end-of-line (BEOL) CMP modeling technology has matured in recent years, FEOL CMP modeling is still facing multiple challenges. This paper describes how an accurate FEOL CMP model may be built, and how interlayer dielectric (ILD) layer CMP simulations may be used for 3D NAND design improvement. In the example of ILD CMP model validation for a 3D NAND product, it is shown that the model predictions match well with the silicon data and that the model may successfully be used for hotspot prediction in production designs prior to manufacturing.
When technology comes to 28nm and beyond, chip size and design complexity are increasing. Lithography simulation is computing intensive and it may takes days to see whether there is any hotspot hard to solve other than change the design. Pattern classification is quite a matured technique and it can be used to locate unique patterns on a chip, then it is possible to do lithography simulation on these unique pattern locations first. This is an efficient approach to quickly detect any unfriendly design style on the layout and give designers enough time to fix these unfriendly designs and do an incremental check to validate the fixing. Once the fixing approach is validated, a pattern matching based pattern substitution can be used to fix all the problematic areas on the layout.
As technology advances, chip size becomes larger and larger, this brings challenges when engineers would like to do a quick investigation of the design in a short time, like hotspot detection and layout fixing. An idea to mitigate the challenges is to decompose a layout into patterns and classify these patterns to unique ones. Engineers then prioritize their work on these unique patterns. Patterns from different products can be accumulated and recorded, when a new design comes in, the known patterns will be filtered out from all unique patterns seen in this new design. When the pattern database is large enough and contains enough safe and weak patterns, machine learning can be used to train the algorithm to predict hotspots in the new design. The key point is how to efficiently decompose a layout and group those patterns. This paper presents how to decompose a layout by using Calibre Pattern Matching and DRC. The experiment data shows that this is a very efficient way to decompose a layout automatically.
Memory is a critical component in today's system-on-chip (SoC) designs. Static random-access memory (SRAM) blocks are assembled by combining intellectual property (IP) blocks that come from SRAM libraries developed and certified by the foundries for both functionality and a specific process node. Customers place these SRAM IP in their designs, adjusting as necessary to achieve DRC-clean results. However, any changes a customer makes to these SRAM IP during implementation, whether intentionally or in error, can impact yield and functionality. Physical verification of SRAM has always been a challenge, because these blocks usually contain smaller feature sizes and spacing constraints compared to traditional logic or other layout structures. At advanced nodes, critical dimension becomes smaller and smaller, until there is almost no opportunity to use optical proximity correction (OPC) and lithography to adjust the manufacturing process to mitigate the effects of any changes. The smaller process geometries, reduced supply voltages, increasing process variation, and manufacturing uncertainty mean accurate SRAM physical verification results are not only reaching new levels of difficulty, but also new levels of criticality for design success. In this paper, we explore the use of pattern matching to create an SRAM verification flow that provides both accurate, comprehensive coverage of the required checks and visual output to enable faster, more accurate error debugging. Our results indicate that pattern matching can enable foundries to improve SRAM manufacturing yield, while allowing designers to benefit from SRAM verification kits that can shorten the time to market.
As integrated circuits (IC) technology moves forward, manufacturing process is facing more and more challenges. Optical proximity correction (OPC) has been playing an important role in the whole manufacturing process. In the deep sub-micron technology, OPC engineers not only need to guarantee the layout designs to be manufacturable but also take a more precise control of the critical patterns to ensure a high performance circuit. One of the tasks that would like to be performed is the consistency checking as the identical patterns under identical context should have identical OPC results in theory, like SRAM regions. Consistency checking is essentially a technique of repeated patterns identification, extraction and derived patterns (i.e. OPC results) comparison. The layout passing to the OPC team may not have enough design hierarchical information either because the original designs may have undergone several layout processing steps or some other unknown reasons. This paper presents a generic way to identify and extract repeated layout structures in SRAM regions purely based on layout pattern analysis through Calibre Pattern Matching and Calibre equation-based DRC (eqDRC). Without Pattern Matching and eqDRC, it will take lots of effort to manually get it done by trial and error, it is almost impossible to automate the pattern analysis process. Combining Pattern Matching and eqDRC opens a new way to implement this flow. The repeated patterns must have some fundamental features for measurement of pitches in the horizontal and vertical direction separately by Calibre eqDRC and meanwhile can be a helper to generate some anchor points which will be the starting points for Pattern Matching to capture patterns. The informative statistical report from the pattern search tells the match counts individually for each patterns captured. Experiment shows that this is a smart way of identifying and extracting repeated structures effectively. The OPC results are the derived layers on these repeated structures, by running pattern search using design layers as pattern layers and OPC results as marker layers, it is an easy job to compare the consistency.
As technology advances, escalating layout design complexity and chip size make defect inspection becomes more challenging than ever before. The YE (Yield Enhancement) engineers are seeking for an efficient strategy to ensure accuracy without suffering running time. A smart way is to set different resolutions for different pattern structures, for examples, logic pattern areas have a higher scan resolution while the dummy areas have a lower resolution, SRAM area may have another different resolution. This can significantly reduce the scan processing time meanwhile the accuracy does not suffer. Due to the limitation of the inspection equipment, the layout must be processed in order to output the Care Area marker in line with the requirement of the equipment, for instance, the marker shapes must be rectangle and the number of the rectangle shapes should be as small as possible. The challenge is how to select the different Care Areas by pattern structures, merge the areas efficiently and then partition them into pieces of rectangle shapes. This paper presents a solution based on Calibre DRC and Pattern Matching. Calibre equation-based DRC is a powerful layout processing engine and Calibre Pattern Matching’s automated visual capture capability enables designers to define these geometries as layout patterns and store them in libraries which can be re-used in multiple design layouts. Pattern Matching simplifies the description of very complex relationships between pattern shapes efficiently and accurately. Pattern matching’s true power is on display when it is integrated with normal DRC deck. In this application of defects inspection, we first run Calibre DRC to get rule based Care Area then use Calibre Pattern Matching’s automated pattern capture capability to capture Care Area shapes which need a higher scan resolution with a tune able pattern halo. In the pattern matching step, when the patterns are matched, a bounding box marker will be output to identify the high resolution area. The equation-based DRC and Pattern Matching effectively work together for different scan phases.
As the IC technology node moves forward, critical dimension becomes smaller and smaller, which brings huge challenge to IC manufacturing. Lithography is one of the most important steps during the whole manufacturing process and litho hotspots become a big source of yield detractors. Thus tuning lithographic recipes to cover a big range of litho hotspots is very essential to yield enhancing. During early technology developing stage, foundries only have limited customer layout data for recipe tuning. So collecting enough patterns is significant for process optimization. After accumulating enough patterns, a general way to treat them is not precise and applicable. Instead, an approach to scoring these patterns could provide a priority and reference to address different patterns more effectively. For example, the weakest group of patterns could be applied the most limited specs to ensure process robustness. This paper presents a new method of creation of real design alike patterns of multiple layers based on design rules using Layout Schema Generator (LSG) utility and a pattern scoring flow using Litho-friendly Design (LFD) and Pattern Matching. Through LSG, plenty of new unknown patterns could be created for further exploration. Then, litho simulation through LFD and topological matches by using Pattern Matching is applied on the output patterns of LSG. Finally, lithographical severity, printability properties and topological distribution of every pattern are collected. After a statistical analysis of pattern data, every pattern is given a relative score representing the pattern’s yield detracting level. By sorting the output pattern score tables, weak patterns could be filtered out for further research and process tuning. This pattern generation and scoring flow is demonstrated on 28nm logic technology node. A weak pattern library is created and scored to help improve recipe coverage of litho hotspots and enhance the reliability of process.
A design usually goes through several versions until achieving a most successful one. These changes between versions are not a complete substitution but a continual improvement, either fixing the known issues of its prior versions (engineering change order) or a more optimized design substitution of a portion of the design. On the manufacturing side, process engineers care more about the design pattern changes because any new pattern occurrence may be a killer of the yield. An effective and efficient way to narrow down the diagnosis scope appeals to the engineers. What is the best approach of comparing two layouts? A direct overlay of two layouts may not always work as even though most of the design instances will be kept in the layout from version to version, the actual placements may be different. An alternative way, pattern based layout comparison, comes to play. By expanding this application, it makes it possible to transfer the learning in one cycle to another and accelerate the process of failure analysis.
This paper presents a solution to compare two layouts by using Calibre DRC and Pattern Matching. The key step in this flow is layout decomposition. In theory, with a fixed pattern size, a layout can always be decomposed into limited number of patterns by moving the pattern center around the layout, the number is limited but may be huge if the layout is not processed smartly! A mathematical answer is not what we are looking for but an engineering solution is more desired. Layouts must be decomposed into patterns with physical meaning in a smart way. When a layout is decomposed and patterns are classified, a pattern library with unique patterns inside is created for that layout. After individual pattern libraries for each layout are created, run pattern comparison utility provided by Calibre Pattern Matching to compare the pattern libraries, unique patterns will come out for each layout. This paper illustrates this flow in details and demonstrates the advantage of combining Calibre DRC and Calibre Pattern Matching.
As technology advances, the need for running lithographic (litho) checking for early detection of hotspots before tapeout has become essential. This process is important at all levels—from designing standard cells and small blocks to large intellectual property (IP) and full chip layouts. Litho simulation provides high accuracy for detecting printability issues due to problematic geometries, but it has the disadvantage of slow performance on large designs and blocks . Foundries have found a good compromise solution for running litho simulation on full chips by filtering out potential candidate hotspot patterns using pattern matching (PM), and then performing simulation on the matched locations. The challenge has always been how to easily create a PM library of candidate patterns that provides both comprehensive coverage for litho problems and fast runtime performance. This paper presents a new strategy for generating candidate real design patterns through a random generation approach using a layout schema generator (LSG) utility. The output patterns from the LSG are simulated, and then classified by a scoring mechanism that categorizes patterns according to the severity of the hotspots, probability of their presence in the design, and the likelihood of the pattern causing a hotspot. The scoring output helps to filter out the yield problematic patterns that should be removed from any standard cell design, and also to define potential problematic patterns that must be simulated within a bigger context to decide whether or not they represent an actual hotspot. This flow is demonstrated on SMIC 14nm technology, creating a candidate hotspot pattern library that can be used in full chip simulation with very high coverage and robust performance.
As technology advances, IC designs are getting more sophisticated, thus it becomes more critical and challenging to fix printability issues in the design flow. Running lithography checks before tapeout is now mandatory for designers, which creates a need for more advanced and easy-to-use techniques for fixing hotspots found after lithographic simulation without creating a new design rule checking (DRC) violation or generating a new hotspot. This paper presents a new methodology for fixing hotspots on layouts while using the same engine currently used to detect the hotspots. The fix is achieved by applying minimum movement of edges causing the hotspot, with consideration of DRC constraints. The fix is internally simulated by the lithographic simulation engine to verify that the hotspot is eliminated and that no new hotspot is generated by the new edge locations. Hotspot fix checking is enhanced by adding DRC checks to the litho-friendly design (LFD) rule file to guarantee that any fix options that violate DRC checks are removed from the output hint file. This extra checking eliminates the need to re-run both DRC and LFD checks to ensure the change successfully fixed the hotspot, which saves time and simplifies the designer’s workflow. This methodology is demonstrated on industrial designs, where the fixing rate of single and dual layer hotspots is reported.
There is an increasing demand for device level layout analysis, especially as technology advances. The analysis is to study standard cells by extracting and classifying critical dimension parameters. There are couples of parameters to extract, like channel width, length, gate to active distance, and active to adjacent active distance, etc. for 14nm technology, there are some other parameters that are cared about. On the one hand, these parameters are very important for studying standard cell structures and spice model development with the goal of improving standard cell manufacturing yield and optimizing circuit performance; on the other hand, a full chip device statistics analysis can provide useful information to diagnose the yield issue. Device analysis is essential for standard cell customization and enhancements and manufacturability failure diagnosis. Traditional parasitic parameters extraction tool like Calibre xRC is powerful but it is not sufficient for this device level layout analysis application as engineers would like to review, classify and filter out the data more easily. This paper presents a fast and efficient method based on Calibre equation-based DRC (eqDRC). Equation-based DRC extends the traditional DRC technology to provide a flexible programmable modeling engine which allows the end user to define grouped multi-dimensional feature measurements using flexible mathematical expressions. This paper demonstrates how such an engine and its programming language can be used to implement critical device parameter extraction. The device parameters are extracted and stored in a DFM database which can be processed by Calibre YieldServer. YieldServer is data processing software that lets engineers query, manipulate, modify, and create data in a DFM database. These parameters, known as properties in eqDRC language, can be annotated back to the layout for easily review. Calibre DesignRev can create a HTML formatted report of the results displayed in Calibre RVE which makes it easy to share results among groups. This method has been proven and used in SMIC PDE team and SPICE team.