Dr. Qinghuang Lin
Director of Technology Development Center at ASML US Inc
SPIE Involvement:
Information Technology Committee | Fellow status | Senior status | Conference Program Committee | Conference Chair | Conference Co-Chair | Journal Editorial Board Member | Editor | Author | Instructor
Publications (29)

SPIE Conference Volume | 25 July 2016

SPIE Conference Volume | 23 April 2015

SPIE Conference Volume | 22 April 2014

SPIE Journal Paper | 23 December 2013
JM3 Vol. 12 Issue 04
KEYWORDS: CMOS technology, Optical lithography, Plasma etching, Etching, Plasma, Semiconductors, Lithography, Extreme ultraviolet, Line edge roughness, Directed self assembly

SPIE Conference Volume | 16 April 2013

Showing 5 of 29 publications
Conference Committee Involvement (27)
Advanced Etch Technology for Nanopatterning IX
25 February 2020 | San Jose, California, United States
Advances in Patterning Materials and Processes XXXVII
24 February 2020 | San Jose, California, United States
Advanced Etch Technology for Nanopatterning VIII
25 February 2019 | San Jose, California, United States
Advances in Patterning Materials and Processes XXXVI
25 February 2019 | San Jose, California, United States
Advances in Patterning Materials and Processes XXXV
27 February 2018 | San Jose, California, United States
Showing 5 of 27 Conference Committees
Course Instructor
SC992: Lithography Integration for Semiconductor FEOL & BEOL Fabrication
Semiconductor fabrication, traditionally including Front-End-Of-The-Line (FEOL), Middle-Of-The-Line, (MOL), and Back-End-Of-The-Line (BEOL), constitutes the entire process flow for manufacturing modern computer chips. The typical FEOL processes include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The MOL is mainly gate contact formation, which is an increasingly challenging part of the whole fabrication flow, particularly for lithography patterning. The BEOL processes include dielectric film deposition, patterning, metal fill and planarization by chemical mechanical polishing. The state-of-the-art semiconductor chips, the so called 7 nm node of Complementary Metal–Oxide–Semiconductor (CMOS) chips, in mass production features the fourth generation three dimensional (3D) FinFET, a minimum metal pitch of about 40 nm and copper (Cu)/low-k interconnects. It is the first generation of logic chips fabricated with extreme ultra-violet (EUV) lithography. The Cu/low-k interconnects are fabricated predominantly with a dual damascene process using plasma-enhanced CVD (PECVD) deposited interlayer dielectric (ILDs), PVD Cu barrier and electrochemically plated Cu wire materials. Successful fabrication and qualification of modern semiconductor chip products requires a deep understanding of the intricate interplay between the materials and the processes employed. This course provides an overview of modern semiconductor fabrication process flow, its integration schemes, fabrication unit processes and key factors affecting yields. It highlights unique challenges in lithography for FEOL, MOL and BEOL and discusses potential solutions as well as practical techniques. The goal of this course is to provide materials, process, integration and lithography engineers a fundamental basis to develop materials and processes for FEOL, MOL and BEOL patterning and to trouble shoot fabrication problems. This course will also introduce new materials (such as high-K/metal gate or HKMG, III-V materials, non-copper BEOL metals), new device and interconnect structures (such as FinFET/ Trigate, nanowires, self-aligned via integration, Cu/air-gap interconnects) and new integrations (such as 3D IC, Through-Silicon Via or TSV, 3D heteogeneous integration) as well as recent advances in lithography technology (such as double patterning, EUV lithography and directed self-assembly, DSA). Implications of these FEOL, MOL and BEOL technologies for lithography will be discussed.
SC833: Lithography Integration for Semiconductor Back-End-Of-The-Line (BEOL)
Semiconductor Back-End-Of-The-Line (BEOL) or interconnect constitutes the bulk of the film stack and the fabrication cost of modern computer chips. The state-of-the-art BEOL features Cu/low-<i>k</i> interconnects with a dielectric constant (<i>k</i>) of the low-<i>k</i> material of less than 3.0. These Cu/low-<i>k</i> interconnects are fabricated predominantly with a dual damascene process using plasma-enhanced CVD (PECVD) deposited interlayer dielectric (ILDs) and PVD Cu barrier materials. Successful fabrication and qualification of modern semiconductor BEOL requires a deep understanding of the intricate interplay between the materials and the processes employed. This course provides an overview of modern semiconductor BEOL, its integration schemes and fabrication processes. It highlights unique challenges in lithography for BEOL and discusses potential solutions as well as practical techniques. The goal of this course is to provide materials and lithography engineers a fundamental basis to develop materials and processes for BEOL patterning and to trouble shoot BEOL fabrication problems.
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